UMTS/HSPA Module Series
UC20 Hardware Design
UC20_Hardware_Design Confidential / Released 36 / 84
Reset pulse
RESET_N
4.7K
47K
≥ 150ms
Figure 12: Reference Circuit of RESET_N by Using Driving Circuit
RESET_N
S2
Close to S2
TVS
Figure 13: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated as the following figure.
V
IL
≤ 0.5V
V
IH
≥ 1.3V
VBAT
150ms
RESETTING
Module
Status
RUNNING
RESET_N
RUNNING
≥ 5s
Figure 14: Timing of Resetting Module