Quectel Smart LTE Module Series, Проектирование аппаратного обеспечения

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Smart LTE Module Series
SC650T Hardware Design
SC650T_Hardware_Design 33 / 131
CSI2_LN0_P 79 AI
MIPI lane 0 data
signal of front
camera (positive)
CSI2_LN1_N 82 AI
MIPI lane 1 data
signal of front
camera (negative)
CSI2_LN1_P 81 AI
MIPI lane 1 data
signal of front
camera (positive)
CSI2_LN2_N 84 AI
MIPI lane 2 data
signal of front
camera (negative)
CSI2_LN2_P 83 AI
MIPI lane 2 data
signal of front
camera (positive)
CSI2_LN3_N 86 AI
MIPI lane 3 data
signal of front
camera (negative)
CSI2_LN3_P 85 AI
MIPI lane 3 data
signal of front
camera (positive)
MCAM_MCLK 99 DO
Master clock signal
of rear camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
SCAM_MCLK 100 DO
Master clock signal
of front camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
MCAM_RST 74 DO
Reset signal of rear
camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
MCAM_
PWDN
73 DO
Power down signal
of rear camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
SCAM_RST 72 DO
Reset signal of front
camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
SCAM_
PWDN
71 DO
Power down signal
of front camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
CAM_I2C_
SCL
75 OD
I2C clock signal of
camera
1.8V power domain.
CAM_I2C_
SDA
76 OD
I2C data signal of
camera
1.8V power domain.
DCAM_MCLK 194 DO
Master clock signal
of depth camera
V
OL
max=0.45V
V
OH
min=1.35V
CAM4_MCLK 236 DO
Master clock signal
of fourth camera
V
OL
max=0.45V
V
OH
min=1.35V
DCAM_RST 180 DO Reset signal of V
OL
max=0.45V