LTE-A Module Series
EG12 Hardware Design
EG12_Hardware_Design 62 / 97
The following figure shows an SDIO interface reference design.
SD Card Connector
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
DETECTIVE
Module
SD_DATA3
SD_DATA2
SD_DATA1
SD_VDD
SD_DATA0
SD_CLK
SD_CMD
SD_DET
R1 0R
R7
100K
R8
100K
R9
100K
R10
100K
R11
100K
R12
470K
VDD_EXT
VDD_2V85
R2 0R
R3 0R
R4 0R
R5 0R
R6 0R
C2
NM
D2 C3
NM
D3 C4
NM
D4 C5
NM
D5
C6
NM
D6
C1
NM
D1
C7
10pF
D7
C8
33pF
C9
100nF
C10
100uF
+
Figure 31: Reference Circuit of SD Card Application
Please follow the principles below in the SD card circuit design:
The voltage range of SD power supply is 2.7V~3.6V and a sufficient current up to 0.8A should be
provided. As the maximum output current of SD_VDD is 50mA which can only be used for SDIO
pull-up resistors, an external power supply is needed for SD card.
To avoid jitter of bus, resistors R7~R11 are needed to pull up the SDIO to SD_VDD. Value of these
resistors is among 10
kΩ~100kΩ and the recommended value is 100kΩ.
In order to improve signal quality, it is recommended to add 0Ω resistors R1~R6 in series between
the module and the SD card. The bypass capacitors C1~C6 are reserved and not mounted by default.
All resistors and bypass capacitors should be placed close to the module.
In order to offer good ESD protection, it is recommended to add a TVS diode on SD card pins.
The load capacitance of SDIO bus needs to be less than 40pF.
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data
trace is 50
Ω (±10%).
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, and analog
signals, as well as noisy signals such as clock signals, and DCDC signals.
It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total trace length inside the module is 36mm, so the
exterior total trace length should be less than 14mm.
Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 40pF.