4 Address Map and Special Registers
This chapter explains how the four UARTs and special registers are
addressed, as well as the layout of those registers. This material will be of interest
to programmers writing driver software for the QSC(LP)-100.
4.1 Base Address and Interrupt Level (IRQ)
The base address and IRQ used by the QSC(LP)-100 are determined by the
BIOS or operating system. Each serial port uses 8 consecutive I/O locations. The
four ports reside in a single block of I/O space in eight byte increments, for a total
of 32 contiguous bytes, as shown in Figure 6.
Base A 24
to Base A 31
Serial 4
Base A 16
to Base A 23
Serial 3
Base A 8
to Base A 15
Serial 2
Base A 0
to Base A 7
Serial 1
I/O Address Range
Port
Figure 6 --- Port Address Map
All four serial ports share the same IRQ. The QSC(LP)-100 signals a
hardware interrupt when any port requires service. The interrupt signal is
maintained until no port requires service. Interrupts are level-sensitive on the PCI
bus.
The base address and IRQ are automatically detected by the device drivers
Quatech supplies for various operating systems. For cases where no device driver
is available, such as for operation under DOS, Quatech supplies the "QTPCI"
DOS software utility for manually determining the resources used. See section
6.3.1 for details.
QSC(LP)-100 User's Manual
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