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Quatech ES-100M, Руководство пользователя

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Line Control Register

This register is located at I/O address [base+3].  It is used for

specifying the format of the asynchronous serial data to be processed by
the UART, and to set the Divisor Latch Access Bit (DLAB) allowing access
to the baud rate divisor latches.

BIT

DESCRIPTION

7

DLAB

 --- Divisor latch access bit:

DLAB must be set to logic 1 to access the baud rate divisor latches.  DLAB must be set
to logic 0 to access the receiver buffer, transmitting holding register and interrupt
enable register.

6

BKCN

 --- Break control:

When set (logic 1), the serial output (SOUT) is forced to the spacing state (logic 0).

5

STKP

 --- Stick parity:

Forces parity to logic 1 or logic 0
if parity is enabled.  

STKP

EPS

PEN

PARITY

x

x

0

None

0

0

1

Odd

0

1

1

Even

1

0

1

Logic 1

1

1

1

Logic 0

4

EPS

 --- Even parity select:

Selects even or odd parity if
parity is enabled.

3

PEN

 --- Parity enable:

Enables parity on transmission
and verification on reception.

2

STB

 --- Number of stop bits:

Sets the number of stop bits
transmitted.

STB

WLS1 WLS0 WORD LEN STOP BITS

0

0

0

5 bits

1

0

0

1

6 bits

1

0

1

0

7 bits

1

0

1

1

8 bits

1

1

0

0

5 bits

1.5

1

0

1

6 bits

2

1

1

0

7 bits

2

1

1

1

8 bits

2

1

WLS1

 ---

Word length select:
Determines the
number of bits per
transmitted word.

0

WLS0

 ---

Figure 20 --- Line Control Register bit definitions

Quatech  QS-100M/ES-100M User's Manual

19

Содержание ES-100M

Страница 1: ...ES 100M QS 100M Multi port Asynchronous Communications Adapter User s Manual QUATECH INC TEL 330 434 3154 662 Wolf Ledges Parkway FAX 330 434 1409 Akron Ohio 44311 BBS 330 434 2481 ...

Страница 2: ...ES 100 User s Manual Version 2 00 October 1994 P N 940 0019 200 ...

Страница 3: ...ogram s In no event will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented herein and in the program s accompanying this document No representation is made regarding the suitability of this product for any particular purpose Quatech Inc reserves the right to edit or append to this document or ...

Страница 4: ...rial Port Functional Description 14 Accessing the Serial Port Registers 15 Interrupt Enable Register 16 Interrupt Identification Register 16 FIFO Control Register 18 Line Control Register 19 Modem Control Register 20 Line Status Register 21 Modem Status Register 22 Scratchpad Register 22 FIFO Interrupt Mode Operation 23 FIFO Polled Mode Operation 24 Baud Rate Selection 25 VII Serial Port Functiona...

Страница 5: ...gure 12 QS 100M ES 100M output connectors 11 Figure 13 Auxiliary signal configuration jumpers 12 Figure 14 Output connector configuration 13 Figure 15 Serial port register address map for 16450 16550 15 Figure 16 Interrupt Enable Register bit definitions 16 Figure 17 Interrupt Identification Register bit definitions 17 Figure 18 Interrupt Identification Register bit decoding 17 Figure 19 16550 FIF...

Страница 6: ...erwise it will act as a 16450 UART The 16550 is suggested for multitasking environments and for applications involving high data rates The QS ES 100M is highly flexible with respect to addressing and interrupt level use The serial ports are addressed in a contiguous block that can be placed anywhere within the range of 0000 hex to FFFF hex and available interrupt levels include IRQ2 to IRQ7 IRQ10 ...

Страница 7: ...s manual for connector details 1 If the default settings are correct skip to step 2 otherwise refer to sections III and IV of this document for detailed information on how to set the address and IRQ level 2 Turn off the power of the computer system in which the QS ES 100M is to be installed 3 Remove the system cover according to the instructions provided by the computer manufacturer 4 Install the ...

Страница 8: ...550 16450 16550 J10 QUATECH INC 16450 16550 16450 16550 16450 16550 16450 16550 J8 J9 J2 J3 J4 J5 J6 J7 J11 J13 J12 J14 J15 J17 J16 J18 Set IRQ level here J10 Shaded parts are not present on the QS 100M ES 100 QS 100M IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 10 IRQ 11 IRQ 12 IRQ 14 IRQ 15 Quatech QS 100M ES 100M User s Manual 3 ...

Страница 9: ... This page left blank intentionally 4 Quatech QS 100M ES 100M User s Manual ...

Страница 10: ... the range of 0000 hex to FFFF hex Each serial port on the QS ES 100M uses 8 consecutive I O locations The ports reside in a contiguous block of I O space in eight byte increments for a total of 32 contiguous bytes in the case of the QS 100M or 64 contiguous bytes in the case of the ES 100M This is shown in Figure 3 PORT ADDRESS RANGE Serial 1 Base Address 0 to Base Address 7 Serial 2 Base Address...

Страница 11: ...n be used to explain the examples shown in Figure 5 Figure 4 Examination of a serial port base address two and one hence the maximum value of 8 4 2 1 15 A serial port s address is a 16 bit quantity that is most often expressed in four hexadecimal base 16 digits A hex digit can hold a value from 0 to 15 decimal and is made up of four binary bits given weights of eight four A possible serial port ad...

Страница 12: ...t status register Another Example 5AC0 hex ON 2 0 8 4 C 1 2 3 4 5 6 SW2 8 0 0 1 5 4 A 1 2 3 4 5 6 SW1 0 0 no digits ES 100M Position 6 of SW2 is used to enable or disable the interrupt status register Factory default setting 0300 hex ON 0 2 0 0 0 1 1 2 3 4 5 6 SW2 0 0 0 0 0 0 3 1 2 3 4 5 6 SW1 0 0 no digits Another Example 5AC0 hex ON 0 2 0 8 4 C 1 2 3 4 5 6 SW2 8 0 0 1 5 4 A 1 2 3 4 5 6 SW1 0 0 n...

Страница 13: ...equires service The interrupt signal is maintained until no port requires service Because the ISA bus is edge sensitive this behavior forces the interrupt service routine to ensure that all ports are checked before exiting A way to do this is to poll each port until an interrupting port is found After servicing the port all ports should be checked again If any interrupting port is left unserviced ...

Страница 14: ...upt status register is non zero The value written is ignored and has no effect on the contents of the interrupt status register Software written to take advantage of this retriggering will be transparent to an older revision of the QS ES 100M BIT DESCRIPTION 7 MSB Serial 8 1 if interrupt pending always 0 on QS 100M 6 Serial 7 1 if interrupt pending always 0 on QS 100M 5 Serial 6 1 if interrupt pen...

Страница 15: ...ations DCEs are unnecessary and in these cases a cable called a null modem cable or modem eliminator cable is used to directly connect two DTE type devices A typical null modem cable is also shown in Figure 10 Figure 10 Cabling requirements for RS 232 C devices cables using 25 pin connectors shown Telephone line DCE DCE DTE DTE RS 232 C RS 232 C Modem Modem Terminal Terminal RxD TxD RTS CTS DTR DS...

Страница 16: ...al Description DTE connection DCE connection RJ 11 D 25 RJ 11 D 25 AuxIn CTS DSR 1 5 6 1 4 20 Transmit Data TxD 2 2 2 3 Chassis Ground Carrier Detect DCD 3 1 8 3 1 8 Signal Ground 4 7 4 7 Receive Data RxD 5 3 5 2 AuxOut DTR RTS 6 20 4 6 6 5 Figure 11 QS ES 100M connector definitions Figure 12 QS ES 100M output connectors D 25 connector using adapter cable 20 21 22 23 24 25 14 15 16 17 18 19 1 2 3 ...

Страница 17: ...ined as well AUXIN may be selected to be either CTS or DSR AUXOUT may be selected to be either RTS or DTR The decision of which signals to use is made separately for each channel Figure 13 Auxiliary signal configuration jumpers 12 Quatech QS 100M ES 100M User s Manual ...

Страница 18: ...his configuration pin 3 of the RJ 11 is connected to chassis ground i e the frame of the PC For applications requiring the carrier detect signal pin 3 of the RJ 11 connector may be configured to input DCD in place of the chassis ground connection The decision to connect pin 3 to chassis ground or DCD may be made on a per channel basis using jumpers J11 through J18 Figure 14 Output connector config...

Страница 19: ...duce the frequency of interrupts issued to the CPU by the UART Other features of the 16450 and 16550 include Programmable baud rate character length parity and number of stop bits Automatic control of start stop and parity bits Independent and prioritized interrupts Transmit clock output receive clock input The QS ES 100M s serial ports are controlled by 16450 or 16550 UARTs The serial ports will ...

Страница 20: ...6550 only on an I O write Also notice that if address base 0 or base 1 is used with the DLAB bit from the Line Control Register set to 1 the baud rate divisor latches are accessed NOTE All figures displaying bitmapped registers are formatted such that bit 7 is the high order bit UART Addressing Register Description DLAB I O Address 0 Base 0 Receive buffer read Transmit holding register write 0 Bas...

Страница 21: ...g Register Empty Interrupt When set logic 1 enables interrupt on transmitter holding register empty 0 ETBEI Received Data Available Interrupt When set logic 1 enables interrupt on received data available For 16550 FIFO mode interrupts are also enabled for receive FIFO trigger level reached and for receive timeout Figure 16 Interrupt Enable Register bit definitions Interrupt Identification Register...

Страница 22: ...rs or break interrupts The interrupt is cleared by reading the line status register 0 1 0 0 2nd Received Data Ready 16450 or 16550 Indicates receive data available The interrupt is cleared by reading the receive buffer In 16550 FIFO mode indicates the receiver FIFO trigger level has been reached The interrupt is reset when the FIFO drops below the trigger level 1 1 0 0 2nd Character Timeout 16550 ...

Страница 23: ...en set logic 1 RxRDY and TxRDY change from mode 0 to mode 1 for DMA transfers DMA mode is not supported on the QS ES 100M 2 XRST Transmit FIFO reset 16550 only When set logic 1 all bytes in the transmitter FIFO are cleared and the counter is reset The shift register is not cleared XRST is self clearing 1 RRST Receive FIFO reset 16550 only When set logic 1 all bytes in the receiver FIFO are cleared...

Страница 24: ... SOUT is forced to the spacing state logic 0 5 STKP Stick parity Forces parity to logic 1 or logic 0 if parity is enabled STKP EPS PEN PARITY x x 0 None 0 0 1 Odd 0 1 1 Even 1 0 1 Logic 1 1 1 1 Logic 0 4 EPS Even parity select Selects even or odd parity if parity is enabled 3 PEN Parity enable Enables parity on transmission and verification on reception 2 STB Number of stop bits Sets the number of...

Страница 25: ...ly connected to the MODEM control outputs and the outputs are forced to the inactive state All characters transmitted are immediately received to verify transmit and receive data paths Transmitter and receiver interrupts still operate normally MODEM control interrupts are available but are now controlled through the MODEM control register 3 OUT2 Output 2 When this bit is set logic 1 the OUT2 outpu...

Страница 26: ...longer than one full word transmission time In 16550 FIFO mode only one zero character is loaded into the FIFO and transfers are disabled until the serial data input goes to the mark state logic 1 and a valid start bit is received 3 FE Framing error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit was a 0 bit spacing level 2 PE Parity erro...

Страница 27: ...input 6 RI Ring indicator Complement of the RI input 5 DSR Data set ready Complement of the DSR input 4 CTS Clear to send Complement of the CTS input 3 DDCD Delta data carrier detect Indicates the Data Carrier Detect input has changed state Cleared when this register is read 2 TERI Trailing edge ring indicator Indicates the Ring Indicator input has changed from a low to a high state Cleared when t...

Страница 28: ...he last read of the FIFO by the CPU was done more than four character times ago 5 Timeout interrupts are cleared when a read of the receive FIFO is done 6 The receive FIFO timeout timer is reset whenever a new character is received into the FIFO or a read of the FIFO is done When The Transmit Fifo And Transmit Interrupts Are Enabled 1 The transmitter holding register empty interrupt occurs when th...

Страница 29: ...s would be done using the Line Status Register 1 The Data Ready bit will be set to logic 1 whenever there is at least one byte in the receive FIFO 2 Errors can be detected using the various error bits 3 The Transmitter Holding Register Empty bit can be used to determine when the transmit FIFO is empty 4 The Transmitter Empty bit indicates that the transmitter shift register is empty as well as the...

Страница 30: ...it to produce the standard clock frequency Jumper block J1 is used to set the frequency input to the UART It may be connected to divide the clock input by 1 2 5 or 10 A table of baud rates available using the 1 8432 MHz input is given in Figure 25 For compatibility with standard serial ports J1 should be configured to divide by 10 as shown in Figure 24 d Figure 24 Input clock frequency options Div...

Страница 31: ... 50 2304 75 1536 110 1047 0 026 150 768 300 384 600 192 1200 96 1800 64 2000 58 0 69 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 2 86 Figure 25 Divisor Latch settings for common baud rates using 1 8432 MHz input clock 26 Quatech QS 100M ES 100M User s Manual ...

Страница 32: ...D 25 connector using optional adapter cables Transmit drivers MC1488 or compatible Receive buffers MC1489 or compatible I O Address range 0000H FFFFH Interrupt levels IRQ2 to IRQ7 IRQ10 to IRQ12 IRQ14 IRQ15 Power requirements QS 100M 5 volts 379 mA typ 448 mA max 12 volts 38 mA typ 46 mA max 12 volts 36 mA typ 43 mA max ES 100M 5 volts 439 mA typ 509 mA max 12 volts 76 mA typ 88 mA max 12 volts 72...

Страница 33: ...of I O space and the ES 100M requires 64 bytes of I O space Set a different address if necessary 3 The QS ES 100M may be defective Contact Quatech Customer Service for instructions Cannot communicate with other equipment 1 Are the cable connections correct Are the cables securely attached 2 Are the base address and interrupt level IRQ correctly set Check for address and IRQ conflicts with other de...

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