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data to pin 4 in all modes except QPSK, UQPSK, AQPSK and AUQPSK, where
it carries the second channel data.
13
Clock 2 Out /
Ones Detector
Out
Secondary 3.3 volt TTL clock output for all modes. This pin carries identical
clock to pin 4 in all modes except QPSK, UQPSK, AQPSK and AUQPSK,
where it carries the second channel clock.
In sync test mode, this pin carries the ones detector output (see section xxx).
14
SDI Out
Signal degradation indicator, for interface to RF Networks model 2241 Diversity
Branch Selector.
15
232 Rx Input
RS-232 commands from host controller.
Table 1. Pin Assignments.
By default, the output data is valid on the falling edge of the clock, as shown in Figure 4.
The polarity of the output clock may be inverted by use of the “CP 1” command (see
below).
Bit period
(360 deg)
User asserts data on rising edge
of TTL clock, rising edge of
ECL clock+ signal, or rizing
edge of TIA/EIA422 "A" clock
generator terminal
Clock jitter and data to clock
skew reference point
Tx samples DATA on
falling edge of TTL clock,
falling edge of EC)
signal, or falling edge of
TIA/EIA422 "A" clock
terminal.
data=1 (MARK)
data=0 (SPACE)
CLOCK
NRZL
DATA
Baseband Signal Timing - 0 degree clock
data=1 (MARK)
Figure 4. Baseband Signal Timing.
The RF input to the receiver module is a 50 Ohm interface, with VSWR less than 1.4:1.
The RDMS also provides a 70 MHz IF output through an SMA connector for
troubleshooting purposes. The IF is resistively coupled from the input of the demodulator.
Therefore, the signal level on the IF output should be within 2 dB of the demodulator’s
input.
The IF output must have a 50-ohm load at all times. Therefore, if it is not connected to
external test equipment, then the 50-ohm terminator that comes installed on the port must
remain attached.
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