QUANTUN QP-650 Plus, Руководство по обслуживанию

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QP-650 Plus Circuit Description
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PLL circuit
Step frequency of PLL can be 2.5 KHz, 5.0 KHz or 6.25 KHz. A 12.8MHz reference oscillator signal
is divided at U610 by a counter to generate a 2.5 KHz, 5.0 KHz or 6.25 KHz reference frequency. Output
signal from VCO is buffer amplified by Q103 and divided at U610 by a frequency divider. The divided
signal is compared with 2.5 KHz, 5.0 KHz or 6.25 KHz reference signal in the phase comparator of U610.
The output signal from phase comparator is filtered through a low pass filter to generate a level D.C., and
the level D.C. controls oscillator frequency by controlling VCO.
VCO
The operating frequency is generated by Q100 in transmit mode and by Q101 in receive mode.
Operating frequency generate a control voltage by phase comparator to control varactor diodes so that
the oscillator frequency is consistent with the MCU preset frequency(D100
、
D101
、
D104 and D105 in
transmit mode, and D102
、
D103
、
D106 and D107 in receive mode). T/R pin is set high level in receive
mode, and low level in transmit mode. The output from Q100 and Q101 is amplified by Q103 and sent to
buffer amplifier.
Unlock detector
An unlock condition appears if low level appears at MUXOUT pin of U610. Transmission is
forbidden if this condition is detected by microprocessor.
3
． ． ． ．
Receiver
The receiver utilizes double conversion superheterodyne
Fig. 3 Receiver Section Configuration