14
5.5
Limitations of the Clk2 output
Read this section very carefully if you intend to use ProgRock’s Clk2 output!
The Si5351A chip contains two PLL circuits and
three output “MultiSynth” divider circuits. The feedback
loop of the PLLs are fractional dividers, and all three output dividers are also fractional. For best
performance (low jitter) the Si5351A datasheet recommends even integers in the “MultiSynth” dividers
even though they are capable of fractional use. However if the PLL A and PLL B are set up for the Clk0
and Clk1 outputs, the only way to permit a general frequency on the Clk2 output, is to use fractional
division in the MultiSynth for Clk2. There are also other limitations on the use of Clk2 because it is used for
calibration when the GPS is connected.
Please take into account the following when considering the use of the Clk2 output:
1)
The Clk2 output is fed via a resistor into the T0 timer input of the microcontroller. However
this pin is also shared with one of the DIP switches S1. When the push-button S2 is pressed,
Clk2 is temporarily disabled so that the state of the DIP switch can be read without
interference.
2)
When using GPS to calibrate and discipline ProgRock, Clk2 cannot be used. A single 1pps
signal pulse on the 1pps input is enough to switch into GPS discipline mode. Clk2 is then
used by the microcontroller for measuring the frequency of the 27MHz reference oscillator.
You must switch off the power and back on again, to get back the use of Clk2. It is strongly
recommended to Ground the 1pps input when not using the GPS option, to prevent
accidental triggering of GPS mode.
3)
Inside the Si5351A, Clk0 is mapped to PLL A. Clk1 is mapped to PLL B. Therefore when you
wish to use Clk2 you MUST ensure that there is a valid frequency set up for Clk1!
4)
There are some frequency limitations imposed by this arrangement. PLL B operates
internally in the Si5351A chip at a frequency of nominally 600-900MHz. The exact PLL VCO
frequency will have been determined by the algorithm that sets up the Si5351A registers for
the specified Clk1 output frequency. For a Clk2 output, the microcontroller specifies a
division ratio to divide PLL B’s output down by a fractional amount to get to the desired Clk2
output frequency. The division ratio must be in the range 8..900. If it is outside this range,
Clk2 will be switched off by the microcontroller. Practically speaking, this limits the frequency
of Clk2 to the range (approximately) 1MHz to 112MHz.
6. Programming
6.1
User Interface
The ProgRock frequencies list is programed in Binary Coded Decimal, which
is input on the 4-way DIP switch, and button. Each time you press the button
briefly, the 3mm red LED will illuminate for a short time. This will give you
positive feedback that your button press actually occurred and the number
programmed on the DIP switch has been accepted by the microcontroller.
You cannot program another digit until the red LED goes off. These basic
