protech PPC-7368, Руководство пользователя

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Chapter 4 Award BIOS Setup
Page: 4-12
PPC-7368 USER
′
S MANUAL
This parameter allows you to configure the system based on the specific
features of the installed chipset. The chipset manages bus speed and
access to system memory resources, such as DRAM and the external cache.
It also coordinates communications between conventional ISA bus and the
PCI bus. It must be stated that these items should never need to be altered.
The default settings have been chosen because they provide the best opera-
ting conditions for the system. The only time you might consider making
any changes would be if you discovered that data was being lost while
using your system.
Please be aware that if select the wrong panel type, it may cause the
abnormal display of the LCD.
DRAM TIMING SELECTABLE :
The value in this field depends on performance parameters of the installed
memory chips (DRAM). Do not change the value from the factory setting
unless you install new memory that has a different performance rating than
the original DRAMs.
DRAM CLOCK :
This item allows you to control the DRAM speed at either equal to or one-
half of the SYSCLK (system clock signal) speed. While speed is always
desirable, choosing the higher setting may prove to be too fast for some
components.
SDRAM CYCLE LENGTH:
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the
default value specified by the system designer.
MEMORY HOLE:
In order to improve performance, certain space in memory is reserved for ISA
cards. This memory must be mapped into the memory space below 16MB.
P2C/C2P CONCURRENCY:
This item allows you to enable/ disable the PCI to CPU, CPU to PCI
concurrency.