Ø
Integrated pull-up, pull-down and series termination resistors on IDE, processor interface
Ø
Integrated Pull-down and Series resistors on USB
Enhanced Hub Interface buffers improve routing flexibility (Not available with all Memory
Controller Hubs)
Firmware Hub (FWH) Interface supports BIOS memory size up to 8 MB
Low Pin Count (LPC) Interface
Ø
Supports two Master/DMA devices.
Enhanced DMA Controller
Ø
Two cascaded 8237 DMA controllers
Ø
PCI DMA: Supports PC/PCI
—
Includes two PC/PCI REQ#/GNT# pairs
Ø
Supports LPC DMA
Ø
Supports DMA collection buffer to provide Type-F DMA performance for all DMA
channels
Real-Time Clock
Ø
256-byte battery-backed CMOS RAM
System TCO Reduction Circuits
Ø
Timers to generate SMI# and Reset upon detection of system hang
Ø
Timers to detect improper processor reset
Ø
Supports ability to disable external devices
SMBus
Ø
New: Hardware packet error checking
Ø
New: Supports SMBus 2.0 Specification
Ø
Host interface allows processor to communicate via SMBus
Ø
Slave interface allows an external microcontroller to access system resources
Ø
Compatible with most 2-wire components that are also I2C compatible
GPIO
Ø
TTL, open-drain, inversion
Package 31x31 mm 421 BGA
D. Clock Generator
TECHNICAL SERVICE MANUAL
Prestigio Nobile 159W
1-10
Содержание NOBILE 159W
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