Portwell WEBS-1108A, Руководство пользователя, Страница: 41 / 74

WEBS-1108A User Manual 41
3.3.3 Advanced Chipset Features
DRAM Clock/Drive Control
When select to “BySPD”, the DRAM timing parameters are set according to DRAM SPD (Serial
Presence Detect). When disabled, one can manually set the DRAM timing parameters through the
sub items below. Set to “BySPD” if not sure.
CAS Latency Time
Controls the latency between the SDRAM Read command and the time data actually becomes
available.
DRAM RAS# to CAS# Delay
Controls the latency between the DDR SDRAM active command and the read/write command.
DRAM RAS# Precharge
Controls the idle clocks after issuing a precharge command to the DDRSDRAM.
Precharge delay (tRAS)
Precharge Delay This setting controls the prechar ge delay, whic h determines the timing delay f or
DRAM precharge.
System Memory Frequency
Allow to choose different frequency of memory module.