Portwell ROBO-503, Руководство пользователя

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ECM-3410/3410L/3410N
ECM-3410/3410L/3410N User’s Manual 113
Appendix E: AWARD BIOS POST Codes
Note: ISA POST codes are outputted to port address 80h
Code (Hex) Name Description
C0 Turn off Chipset Cache OEM Specific-Cache control
1 Processor Test 1 Processor Status (1FLAGS) Verification. Tests the
following processor status flags: carry, zero, sign,
overflow.
The BIOS sets each flag, verifies they are set, then
turns each flagoff and verifies it is off.
2 Processor Test 2 Read/Write/Verify all CPU registers except SS, SP,
and BP with data pattern FF and 00.
3 Initialize Chips Disable NMI, PIE, AIE, UEI, SQWV. Disable video,
parity checking, DMA. Reset math coprocessor.
Clear all page registers, CMOS shutdown byte.
Initialize timer 0, 1, and 2, including set EISA timer to
a known state. Initialize DMA controllers 0 and 1.
Initialize interrupt controllers 0 and 1. Initialize EISA
extended registers.
4 Test Memory
Refresh Toggle
RAM must be periodically refreshed to keep the
memory from decaying. This function ensures that
the memory refresh function is working properly.
5 Blank video, Initialize keyboard Keyboard controller initialization.
6 Reserved
7 Test CMOS
Interface and Battery Status
Verifies CMOS is working correctly, detects bad
battery.
BE Chipset Default Initialization Program chipset registers with power on BIOS
defaults.
C1 Memory presence test OEM Specific-Test to size on-board memory
C5 Early Shadow OEM Specific-Early Shadow enable for fast boot.
C6 Cache presence test External cache size detection
8 Setup low memory Early chip set initialization.
Memory presence test.
OEM chip set routines.
Clear low 64K of memory.
Test first 64K memory.
9 EARLY CACHE INITIALIZATION Cyrix CPU initialization.
Cache initialisation.
A Setup Interrupt Vector Table Initialize first 120 interrupt vectors with
SPURIOUS_INT_HDLR and initialize INT 00h-1Fh
according to INT_TBL.