PEX 8505RDK Hardware Reference Manual v1.1
© 2007, PLX Technology, Inc. All rights reserved.
7
2.5 Reset
Circuitry
The PEX 8505RDK reset circuitry includes a MAX6420 adjustable reset timer (U9) and manual reset
push-button switch (SW6). The reset timer accepts PERST# from the card edge (P1) and from SW6
(logical-OR via U8). The MAX6420 has the capability of adjusting the reset timeout period by changing
the value of C63 (0.001 µF ~= 3 ms).
2.6 Serial
EEPROM
The PEX 8505RDK contains an 8-pin DIP socket for a serial EEPROM (U2). The board is populated with
a blank Atmel AT25080A 8-Kbit device. To use the serial EEPROM, place a shunt between pins 1 and 2
of JP2 (see section 3.4 for more details). The AT25080A device can directly interface to the PEX8505.
2.7 I2C
Interface
The PEX 8505 implements an I2C slave interface, which allows an external I2C master to read and write
device registers through an out-of-band mechanism. The PEX 8505 I2C interface is accessible via a 7-bit
address, at data rates up to 400kbits/sec. The RDK provides two cascaded 2x2, 0.1” pitch headers (JP3
and JP4), which interface to the PEX 8505’s I2C port. This allows for cascading multiple RDKs together
using standard ribbon cable, or connecting various 3
rd
party I2C test equipment such as the Total Phase
Aardvark I2C controller.
Figure 2-3. I2C Connector Orientation for Aardvard I2C Controller
2.8 Power
Distribution
2.8.1 Power
Generation/Conversion
The PEX 8505RDK has two sources for DC power. The first source is the card edge connector (P1),
which gets it’s power from the RDK Port Expander. Card edge power is intended to power only RDK
board components. Slot J1 receives power via a 4-pin ATX hard disk connector (J5).
PEX8505 core and 1.0V supply is derived from the +3.3V rail through a Micrel MIC49150 LDO
regulator (U13). The PEX 8505’s +3.3V I/O supply receives power directly from the +3.3V card edge
power rail. The VTT supply for the PEX8505 PCI Express transmitters, is regulated from the +3.3V card
edge power via a Maxim MAX1806 adjustable LDO regulator (U14). The regulator output voltage is
normally set to +1.50V, but can be adjusted by changing the values of R98 and R102.
The ATX 4-pin connector pr12V and +5V DC power. The +5V is converted down to +3.3V for slot
J1 through a Bel S7AH-08B330/-08E1A0 non-isolated DC/DC converter (U12). The +12V power rail is
used directly.
1
2
1
2
3
3
4
4
JP3
JP4
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