PLX Technology PEX 8505, Справочник по аппаратуре

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PEX 8505RDK Hardware Reference Manual v1.1
2 © 2007, PLX Technology, Inc. All rights reserved.
1.1 PEX 8505 Features
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5-lane, 5-port (maximum) PCI Express switch
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PCI Express Base Specification revision 1.1 and PCI Standard Hot-Plug Controller and
Subsystem Specification, revision 1.0 compliance
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Five PCI Express lanes provide 25 Gbps aggregate bandwidth
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Cut-thru Packet latency of 210ns (x1 to x1)
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Non-blocking internal crossbar architecture supports full wire speed
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Out of band communication/initialization interfaces (Serial EEPROM and I2C)
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Maximum Payload Size up to 1024 bytes
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Performance tuning
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Up to 5-ports (Up to 4 possible port configurations)
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PCI Express Standard Hot Plug Controller for three ports
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Allows any port to be designated as upstream port
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Configuration with strapping pins and/or EEPROM
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Sideband INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) signaling
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Lane reversal
1.2 PEX 8505RDK Features
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PLX PEX 8505 PCI Express switch in a 196-ball PBGA package
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Form factor based on PCI Express Card Electromechanical (CEM) Specification 1.1
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Four downstream PCI Express Slot connectors
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DIP switches for hardware configuration of PEX 8505 and on-board clock circuitry
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Support for Spread Spectrum Clocking (SSC).
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One Hot Plug controllable slot
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Socketable Serial EEPROM (3.3V)
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Standard 0.1” headers to connect up to I2C
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Manual push-button PERST# capability
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Lane Status indicator LEDs for visual inspection of link status
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Auxiliary ATX Hard disk connector for supporting additional power requirements for add-in cards
1.3 RDK Port Expansion Kit Features
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Provides a 4-lane/4-port breakout for PEX 8505 RDKs
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Upstream Connection via standard PCI Express x1cable
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Three downstream PCI Express Slot connectors
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Support for Spread Spectrum Clocking (SSC).
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Standard 0.1” headers to connect up to SM bus
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Manual push-button PERST# capability
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Auxiliary ATX Hard disk connector for supporting additional power requirements for add-in cards