2.
PEX 8112RDK-F System Architecture
The PEX 8112RDK-F assists customers in evaluating PLX Technology’s PEX 8112 PCI Express-to-PCI bridge
device, and to facilitate early development of customer designs with the PEX 8112. The usage configuration is
forward bridging between a PCI Express base board and PCI add-in boards. The PEX 8112RDK-F is designed to
showcase all PEX 8112 features when operating in Forward Bridge mode.
The PEX 8112RDK-F’s form factor is based on the
PCI Local Bus Specification, Revision 3.0
. The PCI interface
supports up to 32-bit transfers, at up to 66 MHz. The PEX 8112RDK-F has four PCI slot (female) connectors –
one straddle mount, and three baseboard mount. Four INT# and four REQ#/GNT# pairs are supported, one for
each slot. The PCI Express interface supports one lane operating at 2.5 Gbps.
The PEX 8112RDK-F +1.5VDC is generated from +3.3 VDC, provided through the PCI Express edge connector.
Limited PCI +5 VDC power is generated from +12 VDC, provided through the PCI Express edge connector.
Limited PCI -12 VDC power is generated from +5 VDC that was generated. PCI +3.3 VDC and +12 VDC are
provided through the PCI Express edge connector. If PCI bus power demands are beyond the capability of
onboard circuitry, PCI bus power can be supplied from a 4-pin hard disk power connector. When in default setting,
plug in the 4-pin hard disk power connector (JP1). This provides the necessary voltages to power up the
PEX 8112RDK-F.
3.3V
5V
VI/O
+12V
-12V
PCI Conn A (J3)
3.3V
5V
VI/O
+12V
-12V
PCI Conn B (J4)
3.3V
5V
VI/O
+12V
-12V
PCI Conn C (J5)
3.3V
5V
VI/O
+12V
-12V
PCI Conn D (J6)
3.3V
12V
PCIe Edge Conn
5V
12V
HDD PWR Conn (JP1)
+5V
►
-12V
DC/DC
+5V
►
+3.3V
DC/DC
1.5V
3.3V
VIO
8112
+3.3V
►
+1.5V
DC/DC
+3.3V
Clock Buf
+3.3V
CPLD
+3.3V
RESET
Logic
PEX8112 Forward Mode RDK
Power Scheme in default setting
PCI Pull-ups
+3.3V
EEPROM
Figure 2. PEX 8112 Forward Mode RDK Power Scheme
PEX 8112RDK-F Hardware Reference Manual for Board Revision 1.0, Version 1.1
© 2008 PLX Technology, Inc. All rights reserved.
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