PLX Technology PEX 8112RDK-F, Справочник по аппаратуре

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PEX 8112RDK-F Hardware Reference Manual for Board Revision 1.0, Version 1.1
8 © 2008, PLX Technology, Inc. All rights reserved.
4. M
ECHANICAL
A
RCHITECTURE
4.1 Monitoring Point, Indicator, Control, and DIP Switch Summary
This section summarizes the interfaces available on the PEX 8112RDK-F for controlling and monitoring PEX 8112
performance.
4.1.1 Monitoring Points
ƒ Six ground post holes, scattered across the PEX 8112RDK-F to provide probe reference points
ƒ Voltages to the PEX 8112 can be monitored at the following locations:
ƒ TP12 (1.5 VCC)
ƒ TP13 (PCI Express 3.3 VCC)
ƒ TP14 (PCI Express 5 VCC)
ƒ PCI bus power can be monitored at the hard disk power connector (JP1)
ƒ J7 – Test points for TCK, TDI, TDO, and TMS
ƒ J9, J10 – footprints of mictor connectors, for PCI bus signal probing.
4.1.2 Indicators
ƒ GPIO indicators – LED[3:0]
4.1.3 Controls
Table 2. PEX 8112RDK-F Default Jumper Settings
Jumper Factory Setting Description
J2 OPEN Pull-up WP# on the serial EEPROM
JP2 2-3 Connect VI/O to 5V
JP3 OPEN Pull-up (1-2) or pull-down (2-3) GPIO0
JP4 OPEN Pull-up (1-2) or pull-down (2-3) GPIO1
JP5 OPEN Pull-up (1-2) or pull-down (2-3) GPIO2
JP6 OPEN Pull-up (1-2) or pull-down (2-3) GPIO3
JP9 OPEN Do not ground INTC#
JP10 OPEN Do not ground INTD#
JP11 OPEN Do not ground INTB#
JP12 OPEN Do not ground INTA#
JP13 1-2 Connect M66EN
JP14 1-2 Pull-up the buffer gate input connected to GPIO2
JP15 1-2 Pull-up the buffer gate input connected to GPIO3
JP16 2-3 FF-OE# drives the buffer OE#
JP17 OPEN Do not ground BAR0ENB#
Note: BAR0ENB# can be set by connecting JP17, or programmed through the serial
EEPROM.
J11 Not installed Hard wire jump 1-2 of J11 for enabling internal PCI arbiter of the PEX 8112
JP8 Not installed JTAG port of U6
JP18 Not installed Hard wire jump 3-5 and 4-6 of JP18 for use of the internal PCI arbiter of PEX 8112