107
XDV-P9
-
Pin Functions (PD4995A)
Pin No.
Pin Name
I/O
Function and Operation
1,2
GND
Digital circuit GND
3
NC
Not used
4
DXTLI
I
27MHz crystal connection terminal which oscillates reference clock signals of
the spindle and PLL
5
DXTLO
O
Not used
6
BUNRI
I
Separation test control terminal for internal RAM
7
TSTSTB
I
Test mode setting input
8
PC2/STB
I/O
Not used
9
PC3/BSYNC
I/O
Not used
10
PC4/SELNED
I
I/O setting terminals for NED (7:0), STM and BSYNC terminals
11
PA7/NED7
I/O
Not used
12
PA6/NED6
I/O
Not used
13
PA5/NED5
I/O
Not used
14
PA4/NED4
I/O
Not used
15
VDD
Digital circuit power supply
16
GND
Digital circuit GND
17
PA3/NED3
I/O
Not used
18
PA2/NED2
I/O
Not used
19
PA1/NED1
I/O
Not used
20
PA0/NED0
I/O
Not used
21
BMODE1
I
Sets which test is done in the test mode
22-25
DD7-4
I/O
DRAM data bus for VBR buffer
26
GND
Digital circuit GND
27
VDD
Digital circuit power supply
28-31
DD3-0
I/O
DRAM data bus for VBR buffer
32
XDCAS
O
DRAM CAS signal for VBR buffer
33
XDWE
O
DRAM WE signal for VBR buffer
34
XDOE
O
DRAM OE signal for VBR buffer
35
XDRAS
O
DRAM RAS signal for VBR buffer
36-38
DA12-10
O
Not used
39-41
DA9-7
O
DRAM address signal for VBR buffer
42
GND
Digital circuit GND
43
VDD
Digital circuit power supply
44-50
DA6-0
O
DRAM address signal for VBR buffer
51,52
GND
Digital circuit GND
53
VDD
Digital circuit power supply
54
XWR
O
Not used
55
XSACK
O
Transfer response terminal for VIDEO_DMA channel
56
SREQ
I
Data transfer request terminal for VIDEO_DMA channel
57-60
SDATA0-3
O
Data output bus for VIDEO=DMA channel
61
GND
Digital circuit GND
62
VDD
Digital circuit power supply
63-66
SDATA4-7
O
Data output bus for VIDEO=DMA channel
67
XAVTRM
O
Signal indicating the head of the sector of the transfer data for VIDEO_DMA
channel
68
BMODE2
I
Sets which test is done in the test mode
69
DMACKI
I
System clock input of DVD/CD ROM data
70
GND
Digital circuit GND
71
DMACKO
O
Outputs reference crystal clock signals of the spindle and PLL
72
XSCL1
I
Chip select signal from the main CPU
73
XSWAIT
O
WAIT output to the main CPU
74
XSRD
I
RD signal for the main CPU
75
XSWR
I
WR signal for the main CPU
76
XSDREQ
O
DMA request for the main CPU
77
SDACK
I
DMA response signal
78
VDD
Digital circuit power supply
79
GND
Digital circuit GND
80-91
SA11-0
I
Main CPU address
92-95
SAD7-4
I/O
Main CPU data bus
96
VDD
Digital circuit power supply
97
GND
Digital circuit GND
98-101
SAD3-0
I/O
Main CPU data bus
Содержание XDV-P9
Страница 6: ...XDV P9 2 2 EXTERIOR 6 ...
Страница 9: ...9 XDV P9 2 3 DVD MECHANISM ...
Страница 25: ...25 XDV P9 IC1201 pin 45 200mV div 10µs div Composite signal output ch1 GND ...
Страница 29: ...29 XDV P9 5V PD6335A 5 6 7 8 A B C D 5 6 7 8 E a E b 2 2 E a 4 5 6 7 8 9 10 ...
Страница 38: ...38 XDV P9 A 1 2 3 4 B C D 1 2 3 4 CLOSE SENSE EJECT RESET G KEYBOARD UNIT G F CN3891 3 5 KEYBOARD UNIT ...
Страница 39: ...39 XDV P9 ...
Страница 41: ...XDV P9 1 2 3 4 A B C D 1 2 3 4 41 B EREF EPVO E MAG SIDE A SIDE B PCB UNIT B B PCB UNIT B B ...
Страница 42: ...42 XDV P9 A 1 2 3 4 B C D 1 2 3 4 C Q851 2 1 9 1 4 1 M M1 CARRIAGE D A E C PCB A ...
Страница 43: ...XDV P9 1 2 3 4 A B C D 1 2 3 4 43 D 1 2 M M2 TRAY C D PCB B ...
Страница 44: ...44 XDV P9 A 1 2 3 4 B C D 1 2 3 4 E E MAIN UNIT E E E E E 4 2 MAIN UNIT ...
Страница 45: ...E E E E E E E 8 14 1 7 45 XDV P9 5 6 7 8 A B C D 5 6 7 8 E SIDE A ...
Страница 46: ...46 XDV P9 A 1 2 3 4 B C D 1 2 3 4 E E DSPCLK IC Q ADJ TC1000 E MAIN UNIT M4 SPDL MOTOR F CN3701 F CN3991 ...
Страница 50: ...50 XDV P9 E E E E E E A 1 2 3 4 B C D 1 2 3 4 F EXTENSION UNIT F ...
Страница 51: ...51 XDV P9 E E E E E E E E E E E E E 5 6 7 8 A B C D 5 6 7 8 F SIDE B ...
Страница 52: ...52 XDV P9 A 1 2 3 4 B C D 1 2 3 4 G CLOSE SENSE EJECT RESET KEYBOARD UNIT G SIDE A 4 4 KEYBOARD UNIT ...
Страница 53: ...53 XDV P9 1 2 3 4 A B C D 1 2 3 4 F CN3891 KEYBOARD UNIT G G SIDE B ...
