PRO-700HD
235
I/O
I
I
I
I
I
I
I
I
I
I
I
—
—
I
I
I
I
I
I
I
I
—
—
I
I
I
I
Pin Name
REFL Y
CY
SUB
UV0
UV1
UV2
UV3
UV4
UV5
UV6
UV7
VDD D1
VSS D1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
AP
SP
MC
LLC
HREF
RESET
7
SAA7165WP (SUB VIDEO ASSY: IC4702)
VIDEO ENHANCEMENT D/A
¶
Pin Assignment
¶
Block Diagram
1
2
3
12
13
22
23
24
26
30
31
32
33
34
35
36
37
38
40
41
42
43
44
V
DDD1
V
DDD2
V
DDA1
V
DDA2
V
DDA3
CUR V
DDA4
MC
LLC
HREF
RESET
SCL
SDA
I
2
C-bus
Y7 to Y0
UV7 to
UN0
YUV-bus
V
SSD1
V
SSD2
AP
SP
SUB
V
SSA1
V
SSA2
V
SSA3
C
Y
Y
REFL
Y
(B - Y)
REFL
UV
C
UV
(R - Y)
25
¶
DAC 3
DAC 2
DAC 1
DATA
SWITCH
SAA7165
DCTI
Y
U
V
PEAKING
AND
CORING
INTERPOLATION
FILTER
Y
FORMATTER
UV
FORMATTER
TIMING
CONTROL
I
2
C-BUS
CONTROL
TEST
CONTROL
21 to 14
11 to 4
data clock
8
8
25
27
28
29
25
¶
25
¶
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
UV3
UV4
UV5
UV6
UV7
Y0
Y2
Y1
Y3
Y
(B - Y)
(R - Y)
SDA
UV2
UV1
UV0
SUB
C
Y
C
UV
V
DDA
V
DDA3
REFL
Y
REFL
UV
CUR
Y4
Y5
Y6
Y7
AP
SP
MC
LLC
HREF
RESET
SCL
V
DDD1
V
SSD1
V
SSA3
V
DDA2
V
SSA2
V
SSA1
V
DDA1
V
DDD2
V
SSD2
SAA7165
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Function
Low reference of luminance DAC (connected to VSS A1)
Capacitor for luminance DAC (high reference)
Substrate (connected to VSS A1)
UV signal input bit UV7 (digital colour-difference signal)
UV signal input bit UV6 (digital colour-difference signal)
UV signal input bit UV5 (digital colour-difference signal)
UV signal input bit UV4 (digital colour-difference signal)
UV signal input bit UV3 (digital colour-difference signal)
UV signal input bit UV2 (digital colour-difference signal)
UV signal input bit UV1 (digital colour-difference signal)
UV signal input bit UV0 (digital colour-difference signal)
+5V digital supply voltage 1
Digital ground 1 (0 V)
Y signal input bit Y7 (digital luminance signal)
Y signal input bit Y6 (digital luminance signal)
Y signal input bit Y5 (digital luminance signal)
Y signal input bit Y4 (digital luminance signal)
Y signal input bit Y3 (digital luminance signal)
Y signal input bit Y2 (digital luminance signal)
Y signal input bit Y1 (digital luminance signal)
Y signal input bit Y0 (digital luminance signal)
Connected to ground (action pin for testing)
Connected to ground (shift pin for testing)
Data cloack CREF (e.g.13.5MHz); at MC=HIGH, the LLC driver-by-two is inactive
Line-locked clock signal (LL27=27MHz)
Data clock for YUV data inputs (for active line 768Y or 640Y long)
Reset input (active LOW)
¶
Pin Function
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