Pioneer MD-P100, Руководство по обслуживанию

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33
MD-P100
Pin No. Pin Name I/O Function and Operation
45 EFMO O FM signal output (Whcn recoding) Not used this set (OPEN)
46 RAOF O Overflow detection signal output of the internal RAM (Decoder monitor out)
RAOF is signal generated when the 32k RAM exceeds the
±
4F jitter margin
Not used this set (OPEN)
47 MVCI I Oscillation input for PLL of the digital in Not used this set (Fixed at “L”)
48 TEST2 I Test terminal input (Fixed at “L”)
49 DIPD O Phase comparator output for PLL of the digital in
When the internal VCO:Frequency;Low
→
”H”
When the external VCO:Frequency;Low
→
”L” Not used this set (OPEN)
50 DVSS1 Ground terminal (Digital system)
51 DICV I Control voltage input terminal of the internal VCO for digital in PLL
52 DIFI I Filter input terminal of the internal VCO for digital in PLL
Not used this set (Fixed at “L”)
53 DIFO O Filter output terminal of the internal VCO for digital in PLL
Not used this set (OPEN)
54 AVDD1 Power supply terminal (+3.3V) (Analog system)
55 ASYO O Playback EFM full-swing output (L=VSS,H=VDD)
56 ASYI I Playback EFM asymmetry comparate voltage input terminal
57 BIAS I Playback EFM asymmetry circuit constant current input terminal
58 RFI I Playback EFM RF signal input from CXA1981AR (IC100)
59 AVSS1 Ground terminal (Analog system)
60 CLTV I VCO control voltage input terminal of the PLL for decoder PLL master clock
61 PCO O Phase comparator output terminal of the PLL for decoder PLL master clock
62 FILI I Filter input terminal of the PLL for decoder PLL master clock
63 FILO O Filter output terminal of the PLL for decoder PLL master clock
64 PEAK I Light amount peak hold signal input from CXA1981AR (IC100)
65 BOTM I Light amount bottom hold signal input from CXA1981AR (IC100)
66 ABCD I Light amount signal input from CXA1981AR (IC100)
67 FE I Focus error signal input from CXA1981AR (IC100)
68 AUX1 I Sub signal input from CXA1981AR (IC100)
69 VC I Center point voltage (1/2 VCC) input from CXA1981AR (IC100)
70 ADIO O Monitor output of the A/D converter input signal Not used this set (OPEN)
71 TEST3 I Test input terminal (Fixed at “L”)
72 AVDD2 Power supply terminal (+3.3V) (Analog system)
73 ADRT I A/D converter action limits (upper side) voltage input (Fixed at “H”)
74 ADRB I A/D converter action limits (lower side) voltage input (Fixed at “L”)
75 AVSS2 Ground terminal (Analog system)
76 SE I Sled error signal input from CXA1981AR (IC100)
77 TE I Tracking error signal input from CXA1981AR (IC100)
78 AUX2 I Sub signal input terminal from CXA1981AR (IC100)
79 DCHG I Connected to the Ground
80 APC I Input terminal for the laser APC Not used this set (Fixed at “L”)
81 TEST1 I Test input terminal (Fixed at “L”)
82 ADFG I ADIP double turned FM signal input from CXA1981AR (IC100)
(22.05kHz
±
1kHz) (TTL schmitt input)
83 TS25 I Test input terminal (Fixed at “L”)
84 LDDR O Laser APC signal output to CXA1981AR (IC100)
85 TRDR O Tracking servo drive signal output (-)
86 TFDR O Tracking servo drive signal output (+)
87 FFDR O Focus servo drive signal output (+)
88 DVDD1 Power supply terminal (+3.3V) (Digital system)
89 FRDR O Focus servo drive signal output (-)
90 FS4 O 176.4kHz clock signal output (MCLK system) Not used this set (OPEN)
91 SRDR O Sled servo drive signal output (+)
92 SFDR O Sled servo drive signal output (-)
93 SPRD O Spindle servo drive signal output (+)
94 SPFD O Spindle servo drive signal output (-)
95 DCLO O Not used (OPEN)