DVR-7000
PU&Mecha
LD
Drv.
H.A.
A2-Chip
DVD-ROM
Enc.
R3-chip
CPU
Writer
FLASH
FLASH
SRAM
SDRAM
DVD-ROM Dec.
& D-Servo
M63
DVD-ROM
Dec.
By-Chip
AV
Decoder
AV-1Chip
Audio I/F
aprilia
(2/2)
Audio
D/A
VQE-5
VQE-3
Y/C/Comp Video Out
Y/Cb/Cr Video Out
Audio Analog Out
DIF Out (Coax, Opt)
ATA-IF
Slalom
Fig. 9 System block diagram
Fig. 10 CPU control share
DMA
I/F
Ouroboros
FL
Tuner/FL
Control CPU
BS/UV
Tuner
/Line
in
3D
Y/C
VIP
George
Audio
A/D
SRC
1394Phy
1394 Link
ceLynx
DDCD
Audery
Audio I/F
aprilia
(1/2)
Graphics
Engine
Vaikilt
MPEG
Video Enc.
&
DVcodec
DVxcel
Main
CPU
Recorder
Tuner, FL, 3D Y/C and
main unit key controls,
Time management and
Timer reserved management
TU/FL
CPU
Serial communication
Main CPU
SH-3
IC1010
Control system wide such as
record / playback operation
including the control of each
CPU and user I/F, etc.
Register access type
communication
Conversion to ATAPI signal
ATAPI I/F
Slalom
IC3003
ATAPI BUS
Communication with
ATAPI command
System control of
Writer UNIT
(DVR-103-PA)
Writer
CPU
SH-2