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27
DJM-900NXS
5
6
7
8
5
6
7
8
A
B
C
D
E
F
[1] Failure in Startup
[1-1] The unit dose not turn on, and the LED of the LFO FORM (WAKE UP) button does not flash.
A
V
+12STBY power failure or MAI
N
_CPU (IC2011) startup error may be suspected.
No.
Cause
Diagnostics Point
Item to be Checked
Corrective Action
Reference
No.
Cause
Diagnostics Point
Item to be Checked
Corrective Action
Reference
No.
Cause
Diagnostics Point
Item to be Checked
Corrective Action
Reference
1
Power failure
MAI
N
Assy
C
N
1202-1pin
Check for the
V
+12STBY power.
• If the
V
+12STBY power cannot be confirmed, go to [2].
• If the
V
+12STBY power can be confirmed, go to [3].
4.3 POWER
BLOCK DIAGRAM
5.3
I
N
FORMATIO
N
O
N
POWER
DIAG
N
OSTICS
2
Power failure
Wire defect
POWER SUPPLY
P3-1pin
Check for the
V
+12STBY power.
• If the
V
+12STBY power can be confirmed,
the wire DKP3901 may be defective. Replace it.
• If the
V
+12STBY power cannot be confirmed,
the POWER SUPPLY Assy may be defective.
Replace it.
3
Power failure
MAI
N
Assy
IC1404-4pin
Check for the
V
+3R3E power.
• If the
V
+3R3E power can be confirmed, go to [4].
• If the
V
+3R3E power cannot be confirmed, the 3.3
V
REGULATOR (IC1404) block may be defective.
Check for the status of soldering and replace it.
4
RESET signal
error
MAI
N
Assy
R2023
Check for the CPU_RESET signal.
• If an output signal can be confirmed, go to [5].
• If an output signal cannot be confirmed, the
RESET IC (IC2010) block may be defective.
Check for the status of soldering and replace it.
10.41 WA
V
EFORMS
MAI
N
ASSY
5
20 MHz CLK
error
MAI
N
Assy
R2019
Check for the 20M_CLK signal.
• If an output signal cannot be confirmed, the
crystal (X2001) block may be defective.
Check for the status of soldering and replace it.
10.41 WA
V
EFORMS
MAI
N
ASSY
6
MAI
N
_CPU
defective
MAI
N
Assy
If the symptom persists after the above
corrections.
The MAI
N
CPU (IC2011) may be defective.
Replace it.
—
[1-2] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) button flashes once.
Communication error between the MAI
N
_CPU (IC2011) and DSP (IC701).
1
DSP (IC701)
does not start.
Devices
• DSP (IC701)
• FLASH (IC703)
• SDRAM (IC702)
MAI
N
Assy
[POWER]
L702
L701
L703
R782
[RESET]
R671
R674
[CLK]
R896
[POWER]
V
+3R3D_DSP
V
+1R2D_DSP
V
+1R2D_DPLL
V
+3R3D_DSP_MEM
[RESET]
DSP_RESET
Check that the signal level of DFLASH_RST
is High.
[CLK]
Check if the 24 MHz clock is input to
24.5M_CLK_DSP.
[POWER]
If an error is detected, check for the power supply
source on the power supply block diagram, and
repair it if it has an error.
[RESET]
If the signal level is not High, check for the signal
supply source of the RESET signal, and repair it if
it has an error.
[CLK]
If no signal is input, check for the signal supply
source of the CLK signal and repair it if it has an
error.
[POWER]
4.3 POWER
BLOCK DIAGRAM
5.3
I
N
FORMATIO
N
O
N
POWER
DIAG
N
OSTICS
[RESET]
10.41 WA
V
EFORMS
MAI
N
ASSY
[CLK]
10.41 WA
V
EFORMS
MAI
N
ASSY
[1-3] The unit does not turn on, and the LED of the LFO FORM (WAKE UP) flashes three times.
Communication error between MAI
N
_CPU (IC2011) and ETHER_ICOM (IC501).
1
ETHER_UCOM
(IC501) does not
start.
Devices
• ETHER UCOM
(IC501)
• FLASH (IC502)
• SDRAM (IC503)
MAI
N
Assy
[POWER]
L502
L501
L503
R613
[RESET]
R673
[CLK]
R2020
[POWER] Check that power at each point
is normal.
V
+1R2D_LA
N
V
+3R3D_LA
N
V
+1R2D_LA
N
_PLL
V
+3R3D_LA
N
_MEM
[RESET]
Check that the signal level of SUB_SH_
RESET is High.
[CLK]
Check if the 20 MHz clock is input to 20M_
CLK_SH.
[POWER]
If an error is detected, check for the power supply
source on the power supply block diagram, and
repair it if it has an error.
[RESET]
If the signal level is not High, check for the signal
supply source of the RESET signal, and repair it if
it has an error.
[CLK]
If no signal is input, check for the signal supply
source of the CLK signal and repair it if it has an
error.
[POWER]
4.3 POWER
BLOCK DIAGRAM
5.3
I
N
FORMATIO
N
O
N
POWER
DIAG
N
OSTICS
[RESET]
10.41 WA
V
EFORMS
MAI
N
ASSY
[CLK]
10.41 WA
V
EFORMS
MAI
N
ASSY
2
FPGA (IC2214)
configuration is
not completed.
Devices
• FPGA (IC2214)
• FLASH (IC502)
MAI
N
Assy
[POWER]
R2239
R2268
R2280
[RESET]
R717
[CLK]
R2304
[Communication line]
R2335
[POWER]
V
+3R3D_FPGA
V
+1R2D_FPGA
V
+3R3D_FPGA_AUX
[RESET]
Check that the signal level of SH_FPGA_
RST_X is High.
[CLK]
Check if the 20 MHz clock is input to 24M_
CLK_FPGA.
[Communication line]
Check that the signal level of SH_FPGA_
DO
N
E is High.
[POWER]
If an error is detected, check for the power supply
source on the power supply block diagram, and
repair it if it has an error.
[RESET]
If the signal level is not High, check for the signal
supply source of the RESET signal, and repair it if
it has an error.
[CLK]
If no signal is input, check for the signal supply
source of the CLK signal and repair it if it has an
error.
[POWER]
4.3 POWER
BLOCK DIAGRAM
5.3
I
N
FORMATIO
N
O
N
POWER
DIAG
N
OSTICS
[RESET]
10.41 WA
V
EFORMS
MAI
N
ASSY
[CLK]
10.41 WA
V
EFORMS
MAI
N
ASSY
[Communication line]
10.41 WA
V
EFORMS
MAI
N
ASSY
1-1
5-1
1-3
1-39
1-39
1-40
1-40
1-55
1-23
1-24
1-25
1-22
1-43
1-43
1-41
1-41
1-50
1-51
1-52
1-30
1-30
1-53
1-53
1-54
1-54
1-56
1-57
1-58
1-26
1-27
1-26 1-27
1-59
1-59
Содержание DJM-900NXS
Страница 10: ...10 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 2 2 PANEL FACILITIES ...
Страница 11: ...11 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Страница 12: ...12 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 ...
Страница 15: ...15 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Страница 20: ...20 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 4 3 DSP BLOCK DIAGRAM ...
Страница 21: ...21 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Страница 87: ...87 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Страница 189: ...189 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F ...
Страница 192: ...192 DJM 900NXS 1 2 3 4 A B C D E F 1 2 3 4 A SIDE B A INPUT ASSY CN4003 CN4002 CN5001 CN5401 ...
Страница 193: ...193 DJM 900NXS 5 6 7 8 5 6 7 8 A B C D E F A SIDE B LF DWX3193 INPUT DWX DNP2625 B CN6201 CN4201 CN4601 1 ...