DEH-P940MP/UC
A
B
C
D
1
2
4
1
2
4
102
-
Pin Functions (PE5269A)
Pin No.
Pin Name
I/O
Format
Function and Operation
1
FTXD
O
C
For rewriting Flash EP-ROM (sending signals)
2
NC
Open
3
BSI
I
Input of P-Bus serial data
4
BSO
O
C
Output of P-Bus serial data
5
bsck
I/O
/C
Input/output of P-Bus serial clock
6, 7
DFS1, 2
O
C
Output 1, 2 of settings of DA I/F IC sampling frequency
8
DCKS
O
C
Output for selection of DA I/F IC clock subharmonic number
9
EVDD
Positive power supply for E power
10
EVSS
Potential of GND of E power
11
NC
Open
12
DCOPY
O
C
Output of settings of DA I/F IC copy flag
13
crst
O
C
Output of reset control of Compression IC
14-16
CBANK0-2
O
C
Output 0-2 of bank settings of Compression IC
17
emph
O
C
Output of information on emphasis
18
DSPMUTE
O
C
Output of DOUT Mute
19
DSET
O
C
Output for lighting the disc set indicator
20
adena
O
C
Output of control of A/D reference voltage supply
21
IC/VPP
IC: connected directly to VSS / VPP: Pull-down
22
BRXEN
I/O
/C
P-Bus receiving enabled
23
bsrq
I/O
/C
Request for P-Bus service request
24
xtalen!
O
C
Output of permission to oscillate CD LSI 16.9344MHz
25
xtalen@
O
C
Output of permission to oscillate CD LSI 24.576MHz
26
xrst
O
C
Output of control of CD LSI reset
27
VDCONT
O
C
Output of control of VD power supply
28
CD3VON
O
C
Output of control of CD +3.3V power supply
29
CONT
O
C
Output of control of power supply to servo driver
30
xwait
I
Input of control signals of CD LSI wait
31
LOEJ
O
C
Output for switching between LOAD/EJECT directions
32
CLCONT
O
C
Output for switching between driver inputs
33
CDMUTE
O
C
Output of control of CD Mute
34
reset
I
Input of system reset
35
XT1
I
Connected to the oscillator for subclock
(connected to VSS via the resistor)
36
XT2
Connected to the oscillator for subclock (Open)
37
REGC
Connected to the capacity stabilizing output of the regulator
(an electrolytic capacitor of about 1
µ
F)
38
X2
Connected to the oscillator for the main clock
39
X1
I
Connected to the oscillator for the main clock
40
VSS
Potential of GND
41
VDD
Positive power supply (5V)
O
C
Output of internal system clock (Open)
O
Output of control signals of CD LSI light
O
Not used (Open)
O
Output of Read/Write control signals of WMA decoder
O
Output of read control signals of CD LSI
O
Output of CD LSI address strobe
I
Input of spindle lock
O
C
Output for reset control of WMA decoder
/C
Address/Data Bus 0-7
B power supply, positive supply (3.3V)
B power supply, potential of GND
/C
Address/Data Bus 8-15
68
xcs
O
C
Output for chip selection of CD LSI
69
wcs
O
C
Output for chip selection of WMA decoder
70, 71
DBBWRDY0, 1
I
Input of write-ready flag with WMA decoder DBBI0, 1
72, 73
DBBRRDY0, 1
I
Input of read-ready flag with WMA decoder DBBO0, 1
74
AVDD
A power supply, positive supply (5V)
75
AVSS
A power supply, potential of GND
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