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CDJ-400
50
1
2
3
4
1
2
3
4
C
D
F
A
B
E
10. SCHEMATIC DIAGRAM
10.1 MAIN ASSY (1/2)
C P U - F P G A
D S P - D A C
DSP-DAC
D B C K
B C K
V
A L I D
B C K
D A T A R 2
D B C K
D A T A L 2
D A T A L 1
S P D I F 0
FPGA-DSP
D A T A 1 2
D A T A 7
D A T A 1 1
D A T A 1 4
D A T A 6
D A T A 1 0
D A T A 1 3
D A T A 9
D A T A 5
D A T A
8
D A T A 1 2
D A T A 4
D A T A 1 5
A D R S 3
A D R S 1 7
ADRESS
A D R E S S
D A T A
8
D A T A 1
D A T A 9
D A T A 2
A D R S 4
A D R S 1 9
X R A S
A D R S 5
A D R S 1 3
A D R S 1 0
X C A S
A D R S 6
A D R S 1 2
A D R S 9
X
W
E S D R A M
A D R S 7
A D R S 1 1
L D Q M
A D R S
8
A D R S 1 4
A D R S 1
8
A D R S 1 5
A D R S 2
A D R S 1 6
D A T A 1 0
A D R S 1
D A T A 1 5
D A T A 3
D A T A 1 4
D A T A 0
D A T A 1 3
D A T A 1 1
A D R S 1 6
A D R S 1 5
A D R S 1 4
A D R S 1 3
A D R S 1 2
A D R S 1 1
A D R S 1 0
A D R S 9
G
N
D D
D A T A 0
D A T A 1
D A T A 2
D A T A 3
D A T A 4
D A T A 5
D A T A 6
D A T A 7
B C L K E
B C L K E
U D Q M
U D Q M
C P U - D S P - D A C
XDSPCS
DSPSI
N
PLAY
A D R S 2 0
D A T A R 1
CPU-BUS
CPU-BUS
X R S T
D A C D A T A
D A C B C K
D A C L R C K
Z E R O
ZERO
D S P R S T
DSPRST
C L K _ D S P 1 6 M
D A C C S
DACCS
MUTE0
X C S F L A S H
X C S S D R A M
R X / X B Y
C P U - B U S
A D R S 1
8
A D R S 1 9
S P D I F 0
S P D I F 0
C L K _ D A C 1 1 M
A D R S 2 2
A D R S 2 0
A D R S 2 1
A D R S 2 3
A D R S 2 5
T A
P S T 2
P S T 0
P S T C L K
P S T 3
P S T 1
T M S B K P T
T C K D S
T D I D S I
T D O D S O
DACDATA
D A C L R C K
D A C B C K
DATA
8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
D A T A 7
D A T A 6
D A T A 5
D A T A 4
D A T A 3
D A T A 2
D A T A 1
D A T A 0
C L K _ D S P 1 6 M
V
A L I D
D B C K
TSCK
D A T A L 1
D A T A R 1
D A T A L 2
D A T A R 2
TSI
TSO
TSCS
P
W
MSL1I
N
P
W
M S L 1 I
N
P
W
MSL2I
N
P
W
M S L 2 I
N
S R
V
S D A T A
S R
V
L R C K
P
W
M L O
PRGM
ADRS5
ADRS4
ADRS3
X I
N
I T
F P G A L R C K
F P G A S C L K
F P G A S D A T A
F P G A S B S Y
F P G A D R E Q
X C S F P G A
A D R S 1
A D R S 2
B C K
SR
V
SCLK
S R
V
S C L K
A _ A R O U T 0
A _ A L O U T 0
DATA
D A T A
X F R S T
C L K _ D A C 1 1 M
C L K _ F P 1 6 M
V
+ 2 R 5
G
N
DD
C129
0.1
C132
0.1
C145
0.1
C146
0.1
C 1 2 1
0 . 1
C 1 2 0
0 . 1
C 1 1 9
0 . 1
C131
0.1
C130
0.1
C13
8
0.1
C139
0.1
C 1 5 5
0 . 1
C 1 5 4
0 . 1
C 1 5 3
0 . 1
C 1 5 2
0 . 1
S R
V
S B S Y
F r o m S R
V
CLK_SR
V
16M
to SR
V
Q S P I S C K
F r o m C P U
QSPISO
From CPU
C137
0.1u
C 1 1 0
0 . 1 u
C133
0.1u
C127
0.1u
Q S P I S O
F r o m C P U
Q S P I S C K
F r o m C P U
R121
22k
C 1 1 2
0 . 1 u
Q S P I S O
F r o m C P U
G
N
DD
Q S P I S C K
F r o m C P U
D S P D R E Q
t o C P U & F P G A
C 1 4 2
0 . 1 u
C122
0.1u
R 1 2 6
2 2 k
C12
8
0.1u
C134
0.1u
C 1 4 0
0 . 1 u
C 1 1 1
0 . 1 u
C 1 4 1
0 . 1 u
X
W
E
F r o m C P U
CLK_70M
From CPU
V
+ 3 R 3
I C 1 1 0
B D 0 0 K A 5
W
F P - T L B
1
CTL
2
V
cc
3
N
C
4
OUT
5
ADJ
C164
0.1u
C160
0.1u
I O _ L 0 1 P _ 7 /
V
R
N
_ 7
1
1 :
I O _ L 0 1
N
_ 7 /
V
R P _ 7
2
2 :
G
N
D 1
3
3 :
I O _ L 2 1 P _ 7
4
I O _ L 2 1
N
_ 7
5
V
C C O _ 7
6
V
C C A U X 1
7
I O _ L 2 3 P _ 7
8
I O _ L 2 3
N
_ 7
9
G
N
D 2
1 0
I O _ L 4 0 P _ 7
1 1
I O _ L 4 0
N
_ 7 /
V
R E F _ 7
1 2
I O _ L 4 0 P _ 6 /
V
R E F _ 6
1 3
I O _ L 4 0
N
_ 6
1 4
I O _ L 2 4 P _ 6
1 5
I O _ L 2 4
N
_ 6 /
V
R E F _ 6
1 6
I O 1
1 7
V
C C I
N
T 1
1
8
V
C C O _ 6
1 9
G
N
D 3
2 0
I O 2
2 1
I O _ L 0 1 P _ 6 /
V
R
N
_ 6
2 2
2 2 :
I O _ L 0 1
N
_ 6 /
V
R P _ 6
2 3
2 3 :
M 1
2 4
2 4 :
M 0
2 5
2 5 :
M2
26
IO_L01P_5/CS_B
27
IO_L01
N
_5/RD
W
R_B
2
8
G
N
D4
29
IO_L2
8
P_5/D7
30
V
CCO_5
31
IO_L2
8N
_5/D6
32
V
CCAUX2
33
IO_L31P_5/D5
34
IO_L31
N
_5/D4
35
IO_L32P_5/GCLK2
36
IO_L32
N
_5/GCLK3
37
IO_L32P_4/GCLK0
3
8
IO_L32
N
_4/GCLK1
39
IO_L31P_4/DOUT/BUSY
40
G
N
D5
41
IO_L31
N
_4/I
N
IT_B
42
IO_L30P_4/D3
43
IO_L30
N
_4/D2
44
V
CCI
N
T2
45
45:
V
CCO_4
46
46:
IO_L27P_4/D1
47
47:
IO_L27
N
_4/DI
N
/D0
4
8
4
8
:
IO_L01P_4/
V
R
N
_4
49
49:
IO_L01
N
_4/
V
RP_4
50
50:
D O
N
E
5 1
C C L K
5 2
I O _ L 0 1 P _ 3 /
V
R
N
_ 3
5 3
I O _ L 0 1
N
_ 3 /
V
R P _ 3
5 4
I O 3
5 5
G
N
D 6
5 6
V
C C O _ 3
5 7
V
C C A U X 3
5
8
I O 4
5 9
I O _ L 2 4 P _ 3
6 0
I O _ L 2 4
N
_ 3
6 1
I O _ L 4 0 P _ 3
6 2
I O _ L 4 0
N
_ 3 /
V
R E F _ 3
6 3
I O _ L 4 0 P _ 2 /
V
R E F _ 2
6 4
I O _ L 4 0
N
_ 2
6 5
G
N
D 7
6 6
I O _ L 2 4 P _ 2
6 7
I O _ L 2 4
N
_ 2
6
8
V
C C I
N
T 3
6 9
V
C C O _ 2
7 0
I O _ L 2 1 P _ 2
7 1
I O _ L 2 1
N
_ 2
7 2
G
N
D
8
7 3
I O _ L 0 1 P _ 2 /
V
R
N
_ 2
7 4
7 4 :
I O _ L 0 1
N
_ 2 /
V
R P _ 2
7 5
7 5 :
TDO
76
TCK
77
TMS
7
8
IO_L01P_1/
V
R
N
__1
79
IO_L01
N
_1/
V
RP__1
8
0
IO5
8
1
G
N
D9
8
2
V
CCO_1
8
3
V
CCAUX4
8
4
IO_L31P_1
8
5
IO_L31
N
_1/
V
REF_1
8
6
IO_L32P_1/GCLK4
8
7
IO_L32
N
_1/GCLK5
88
IO_L32P_0/GCLK6
8
9
IO_L32
N
_0/GCLK7
90
IO_L31P_0/
V
REF_0
91
IO_L31
N
_0
92
V
CCI
N
T4
93
V
CCO_0
94
G
N
D
95
IO_L01P_0/
V
R
N
_0
96
IO_L01
N
_0/
V
RP_0
97
HS
W
AP_E
N
9
8
PROG_B
99
TDI
100
C 1 0
8
0 . 1 u
C 1 0 1
0 . 1 u
C 1 0 6
0 . 1 u
C 1 0 3
0 . 1 u
X
W
E
F r o m C P U
C L K _ 7 0 M
F r o m C P U
C 1 0 7
0 . 1 u
C 1 0 5
0 . 1 u
X O E
F r o m C P U
V
+ 3 R 3
C 1 0 2
0 . 1 u
C 1 0 9
0 . 1 u
G
N
DD
G
N
DD
R 1 0 2
2 2 k
R 1 0 4
2 2 k
V
+ 2 R 5
G
N
DD
R 1 1 2
N
M
R 1 0 7
0
X O E
F r o m C P U
G
N
DD
D S P D R E Q
F r o m D S P
SR
V
-FPGA
CLK_CPU16M
to CPU
R 1 3 9
4 7 0
R114
470
IC102
K4S561632H-UC75
V
D D 1
1
D Q 0
2
V
D D Q 1
3
D Q 1
4
5
D Q 2
6
V
S S Q 1
7
D Q 3
8
D Q 4
9
V
D D Q 2
1 0
D Q 5
1 1
D Q 6
1 2
V
S S Q 2
1 3
D Q 7
1 4
V
D D 2
1 5
L D Q M
1 6
W
E
1 7
C A S
1
8
R A S
1 9
C S
2 0
B A 0
2 1
B A 1
2 2
A 1 0 / A P
2 3
A 0
2 4
A 1
2 5
A 2
2 6
A 3
2 7
V
D D 3
2
8
V
S S 1
2 9
A 4
3 0
A 5
3 1
A 6
3 2
A 7
3 3
A
8
3 4
A 9
3 5
A 1 1
3 6
A 1 2
3 7
C K E
3
8
C L K
3 9
U D Q M
4 0
N
. C / R F U
4 1
V
S S 2
4 2
D Q
8
4 3
V
D D Q 3
4 4
D Q 9
4 5
D Q 1 0
4 6
V
S S Q 3
4 7
D Q 1 1
4
8
D Q 1 2
4 9
V
D D Q 4
5 0
D Q 1 3
5 1
D Q 1 4
5 2
V
S S Q 4
5 3
D Q 1 5
5 4
V
S S 3
V
+ 3 R 3
V
- 5
G
N
DD
V
+ 3 R 3
R120
10k
R119
10k
R11
8
10k
R117
10k
BCKI
N
1
DATA
2
LRCKI
N
3
G
N
D
4
5
V
dd
6
V
cc
7
V
outL
8
V
outR
9
AG
N
D
10
V
com
11
ZEROR
12
ZEROL
13
MD
14
MC
15
ML
16
MCLK
R105
10k
C117
0.1u
V
+ 3 R 3 A
V
+ 1 R 2 5
C123
0.1u
G
N
DD
Q 1 0 2
2 S C 2 4 1 2 K ( R S )
R144
1.
8
k
R145
3.9k
R147
220
G
N
DD
C 1 6 1
0 . 0 1 u
G
N
DD
I C 1 0 7
N
J M 4 5
8
0 M D
3
4
2
1
8
I C 1 0 7
N
J M 4 5
8
0 M D
5
4
6
7
8
V
+ 5 A
V
- 5
C 1 5 1
0 . 1 u
R150
22k
F
G
N
DD
G
N
DD
C 1 4 9
0 . 1 u
G
N
DD
G
N
DD
V
+ 1 R 2 5
V
+ 3 R 3
M M 1 5 6 2 F F
I C 1 0 4
V
o u t
1
N
C
2
G
N
D
3
C n
4
5
C o n t
6
S u b
7
V
i n
C156
0.1u
I C 1 0
8
B D 0 0 K A 5
W
F P - T L B
1
CTL
2
V
cc
3
N
C
4
OUT
5
ADJ
C150
0.1u
V
+ 3 R 3
C114
0.1u
C125
1u
G
N
DD
G
N
DD
V
+ 3 R 3
V
+ 1 R 2
C 1 1
8
0 . 1
R 1 0 3
2 2 k
V
+ 3 R 3
G
N
DD
C 1 6 3
0 . 1
X 1 0 1
V
S S 1 0
8
4 - A
R 1 4
8
1 M
G
N
DD
C 1 5 7
0 . 1
V
+ 3 R 3
R140
33k
F
R141
56k
F
G
N
DD
G
N
DD
TFM-115-32-S-D
N
M
1
G
N
D D
2
G
N
D D
3
R S
V
D
4
T M S B K P T
5
G
N
D D
6
T C K D S
7
G
N
D D
8
R S
V
D
9
X R S T
1 0
T D I D S I
1 1
V
+ 3 R 3
1 2
T D O D S O
1 3
G
N
D D
1 4
P S T 3
1 5
P S T 2
1 6
P S T 1
1 7
P S T 0
1
8
D T 3
1 9
D T 2
2 0
D T 1
2 1
D T 0
2 2
G
N
D D
2 3
R S
V
D
2 4
R S
V
D
2 5
G
N
D D
2 6
P S T C L K
2 7
V
+ 3 R 3
2
8
T A
2 9
G
N
D D
3 0
G
N
D D
R156
6
8
R151
33k
F
SDO4_SDI1_PC7
1
IO_G
N
D_1
2
IO_
V
DD_1
3
SDO3_SDI2_PC
8
4
SDO2_SDI3_PC9
5
SDO1_PC10
6
SDO0_PC11
7
CORE_
V
DD_1
8
PF
8
9
PF6
10
PF7
11
CORE_G
N
D_1
12
PF2
13
PF3
14
PF4
15
PF5
16
IO_
V
DD_2
17
PF1
1
8
PF0
19
IO_G
N
D_2
20
P F 9
2 1
2 1 :
S C A
N
2 2
2 2 :
P F 1 0
2 3
2 3 :
I O _ G
N
D _ 3
2 4
I O _
V
D D _ 3
2 5
T I O 0 _ P B 0
2 6
T I O 1 _ P B 1
2 7
C O R E _ G
N
D _ 2
2
8
C O R E _
V
D D _ 2
2 9
T D O
3 0
T D I
3 1
T C K
3 2
T M S
3 3
M O S I _ H A 0
3 4
M I S O _ S D A
3 5
S C K _ S C L
3 6
S S _ H A 2
3 7
H R E Q
3
8
3
8
:
P L L A _
V
D D
3 9
3 9 :
P L L A _ G
N
D
4 0
4 0 :
PLLP_
V
DD
41
PLLP_G
N
D
42
PLLD_G
N
D
43
PLLD_
V
DD
44
EXTAL
45
PI
N
IT_
N
MI
46
RESET_B
47
MODD_IRQD
4
8
MODC_IRQC
49
MODB_IRQB
50
MODA_IRQA
51
CORE_
V
DD_3
52
CORE_G
N
D_3
53
SDO0_PE11
54
SDO1_PE10
55
SDO2_SDI3_PE
56
SDO3_SDI2_PE
57
SDO4_SDI1_PE
5
8
SDO5_SDI0_PE
59
FST_PE4
60
F S R _ P E 1
6 1
6 1 :
S C K T _ P E 3
6 2
6 2 :
S C K R _ P E 0
6 3
6 3 :
I O _
V
D D _ 4
6 4
6 4 :
I O _ G
N
D _ 4
6 5
6 5 :
H C K T _ P E 5
6 6
H C K R _ P E 2
6 7
C O R E _ G
N
D _ 4
6
8
A D O _ P D 1
6 9
A C I _ P D 0
7 0
C O R E _
V
D D _ 4
7 1
H C K R _ P C 2
7 2
H C K T _ P C 5
7 3
I O _ G
N
D _ 5
7 4
I O _
V
D D _ 5
7 5
S C K R _ P C 0
7 6
7 6 :
S C K T _ P C 3
7 7
7 7 :
F S R _ P C 1
7
8
7
8
:
F S T _ P C 4
7 9
7 9 :
S D O 5 _ S D I 0 _ P C 6
8
0
8
0 :
C 2 0 4
0 . 1 u
V
+ 3 R 3
R197
220
X 1 0 2
V
S S 1 2 1 0 - A
G
N
DD
V
+ 3 R 3
C 2 0
8
0 . 1
R123
47k
D
R122
47k
D
R 1 2 5
4 7 0 D
R 1 2 4
4 7 0 D
R 1 3 1
1 . 5 k
D
R 1 2
8
1 . 5 k
D
R132
1.5k
D
R 1 3 6
1 1 k D
R 1 3 0
1 0 k D
C 2 0 9
5 6 0 p
R 1 3 5
1 1 k D
R 1 2 7
1 0 k D
R129
1.5k
D
C 2 1 0
5 6 0 p
R149
39
R 1 0 9
2 . 7 k
R101
10k
C 1 4 7
4 7 0 p
C116
470p
C143
470p
C144
470p
C 1 4
8
4 7 0 p
R 1 9
8
1 M
I C 1 1 7
T C 7 S U 0 4 F U
N
C
1
I
N
A
2
G
N
D
3
O U T Y
4
5
V
C C
I C 1 1 1
T C 7 S U 0 4 F U
N
C
1
I
N
A 2
G
N
D
3
O U T Y
4
5
V
C C
I C 1 0 9
T C 7
W
0 4 F U - T R B
1
1 A
2
3 Y
3
2 A
4
G
N
D
5
2 Y
6
3 A
7
1 Y
8 V
C C
R T 1 P 2 4 1 M
Q 1 0 1
R T 1
N
2 4 1 M
Q 1 0 3
22u/6.3
C115
22u/6.3
C15
8
22u/6.3
C166
1 0 0 u / 6 . 3
C 1 6 2
100u/6.3
C135
100u/6.3
C136
1 0 0 u / 1 6
C 2 0 5
1 0 0 u / 1 6
C 2 1 1
1 0 0 u / 1 6
C 2 1 2
10u/16
C124
V
+ 7 M
IC101
S29AL016D70TFI010
DY
W
1763-
A 1 5
1
A 1 4
2
A 1 3
3
A 1 2
4
5
A 1 1
6
A 1 0
7
A 9
8
A
8
9
A 1 9
1 0
N
C 1 0
1 1
/
W
E
1 2
/ R E S E T
1 3
N
C 1 3
1 4
N
C 1 4
1 5
R Y _ / B Y
1 6
A 1
8
1 7
A 1 7
1
8
A 7
1 9
A 6
2 0
A 5
2 1
A 4
2 2
A 3
2 3
A 2
2 4
A 1
2 5
A 0
2 6
/ C E
2 7
V
S S _ 2 7
2
8
/ O E
2 9
D Q 0
3 0
D Q
8
3 1
D Q 1
3 2
D Q 9
3 3
D Q 2
3 4
D Q 1 0
3 5
D Q 3
3 6
D Q 1 1
3 7
V
C C _ 3 7
3
8
D Q 4
3 9
D Q 1 2
4 0
D Q 5
4 1
D Q 1 3
4 2
D Q 6
4 3
D Q 1 4
4 4
D Q 7
4 5
D Q 1 5 _ A - 1
4 6
V
S S _ 4 6
4 7
/ B Y T E
4
8
A 1 6
C159
1
8
p
CH
C165
1
8
p
CH
I C 1 2 0
N
J M 2
8
7 2 B F 3 3
V
I
N
1
G
N
D
2
C O
N
T R O L
3
N
B
4
5
V
O U T
C214
1u
C215
0.1u
C216
0.01u
I C 1 1 9
N
J M 2
8
7 2 B F 0 5
V
i n
1
G
N
D
2
C O
N
T R O L
3
4
5
V
o u t
V
+ 3 R 3 A
C217
1u
C21
8
0.01u
R146
1k
R199
2.2k
C207
1
8
pC
H
C206
1
8
p
CH
C 2 2 0
0 . 1 u
22u/6.3
C113
R116
22k
C126
0.47u
IC106
XC3S50-4
V
QG100C
PCM1742KE
IC103
DSPC56371AF1
8
0
IC105
!
!
!
!
!
!
S T B Y
7 0 M H z
7 0 M H z
1 1 M
G
N
D D
FPGA
DSP
DAC
FLASH ROM(16M)
SDRAM(256M)
F P 1 6 M
D S P 1 6 M
L c h
R c h
1 6 . 9 3 4 4 M H z
C P U 1 6 M
6 M H z
16.9344M
1 6 . 9 3 4 4 M
1 6 . 9 3 4 4 M
1 6 . 9 3 4 4 M
V
+ 5 A
6 M 0
A L O
A R O
S P D 0
S P D 1
V
1 R 2 5
V
3R3
P F 9
T D O
T D I
T M S
T C K
PE7
PE10
PE11
PE
8
PE9
P E 3
V
1 R 2
V
3 R 3
T D O
TCK
TMS
T D I
V
2 R 5
V
3 R 3
1 6 M
N
B
N
M
m e a n s S T A
N
D B Y
R S 1 / 1 6 S S * * * * F
C E
V W
o r C E H
V W
C K S S Y B
R S 1 / 1 6 S S * * * J
C H
N
O T E S
C C S S C H
F
D
R S 1 / 1 6 S S * * * * D
T h e m a r k f o u n d o n s o m e c o m p o n e n t p a r t s s h o u l d b e r e p l a c e d
w i t h s a m e p a r t s ( s a f e t y r e g u l a t i o n a u t h o r i z e d ) o f i d e n t i c a l
d e s i g n a t i o n
MUTE
CURCUIT
REGULATOR
1.25
V
AUDIO
FILTER
REGULATOR
1.2
V
REGULATOR
2.5
V
REGULATOR
5.0
V
REGULATOR
3.3
V
FILTER
OSC
OSC
2/2
A
2/2
A
2/2
A
C
N
101
30
31
28
29
27
26
20
21
22
23
24
25
A
1/2
40
37
38
46
44
39
2
(Data)
(Data)
(Anal)
(Anal)
32
35
48
42
33
34
49
46
-b
48
-b
-a
-a
19
45
-a
47
41
43