67
BDP-LX55
5
6
7
8
5
6
7
8
A
B
C
D
E
F
A
12/15
ALL POWER/GND BALLS SHOULD GO TO
POWER/GND PLANES THROUGH VIAS ONLY
(NO TRACKS)
Single VIA
to GND
pl
a
ne
closest to
c
a
ps
C155,C156 & R62
sho
u
ld be pl
a
ced
close to Y1
ATEST & TDO
ON BERG
PINS FOR
DEBUG
TEST=LOW
FOR NORMAL
OPERATION
Cb0/Cr0
CLK, DATA
&
CONTROLS
SHOULD BE
LENGTH
MATCHED.
SIL 91
3
6
N
ER
OPEN
Y0--Y9
DATAOUT0---DATAOUT9
DATAOUT10---DATAOUT19
Cb9/Cr9
---
Sign
a
l
DATA
3
V
3
_KYOTO_G2
1V
8
_KYOTO_G2_DDR2
3
.
3
V
1V_KYOTO_G2
1V
8
_FOR_Xt
a
l
1V
8
_KYOTO_G2_DDR2
3
.
3
V
1V
8
_KYOTO_G2_DDR2
1V
8
_FOR_Xt
a
l
MCU_SCL
16 14
MCU_SDA
16 14
QDEO__REST
16
HSOUT1 14
VSOUT1 14
FDOUT1 14
CLKOUT1 14
DATAOUT[19:0]
14
C4
4
3
N
C
/100pF/
50V/
NP0
C4
4
3
N
C
/100pF/
50V/
NP0
4.7K
R92
R
111
4.
7K
R
111
4.
7K
R95
100
R95
100
R9
3
4.7K
R9
3
4.7K
R77
4.7K
R77
4.7K
R97
100
R97
100
R91
4.7K
R91
4.7K
R9
8
1M
R9
8
1M
C156
27pF/50V/NP0
U14C
88
DE2750
U14C
88
DE2750
MVDD
J5
MVDD
K5
MVDD
L5
MVDD
M5
MVDD
N4
MVDD
P
3
MVDD
R2
IOVDD
A16
IOVDD
B6
IOVDD
B15
IOVDD
C14
IOVDD
D1
3
DVDD
F5
DVDD
G5
MVDD
H
3
DVDD
H4
DDR_AVDD
T4
PVDDA
N12
PVSSA
P12
XTVSS
R1
3
MVDD
T1
MVDD
M6
MVDD
M7
MVDD
M
8
MVDD
T
8
MVDD
R9
MVDD
T11
MVDD
R12
MVDD
M1
DVDD
E9
IOVDD
E10
IOVDD
E11
IOVDD
E12
IOVDD
F2
IOVDD
F12
IOVDD
F15
IOVDD
G12
IOVDD
H12
IOVDD
J12
IOVDD
J14
IOVDD
K16
IOVDD
M16
IOVDD
P16
IOVDD
A1
3
DVDD
H5
DVDD
K12
DVDD
L12
DVDD
M9
DVDD
M10
DVDD
M11
DVDD
M12
DVDD
M14
DVDD
R15
DVDD
R16
DVDD
T15
DVDD
T16
DVDD
P14
DVDD
N1
3
VSS
A1
VSS
B2
VSS
C
3
VSS
D4
DVDD
D
8
VSS
E6
VSS
E5
VSS
E7
DVDD
E
8
VSS
E14
VSS
F6
VSS
F7
VSS
F
8
VSS
F9
VSS
F10
VSS
F11
VSS
G6
VSS
G7
VSS
G
8
VSS
G9
VSS
G10
VSS
G11
VSS
H6
VSS
H7
VSS
H
8
VSS
H9
VSS
H10
VSS
H11
VSS
H15
VSS
J6
VSS
J7
VSS
J
8
VSS
J9
VSS
J10
VSS
J11
VSS
K6
VSS
K7
VSS
K
8
VSS
K9
VSS
K10
VSS
K11
VSS
L6
VSS
L7
VSS
L
8
VSS
L9
VSS
L10
VSS
L11
VSS
L2
VSS
M1
3
VSS
M15
VSS
N11
VSS
R1
VSS
R5
VSS
R
8
VSS
R10
VSS
R14
VSS
T12
IOVDD
D9
MVDD
K2
VSS
J1
C155
27pF/50V/NP0
C
3
74
10P/50V/NP0
C
3
74
10P/50V/NP0
C145
0.
1
u
F/
16V/
X
7R
BERG-PIN1
BERG-PIN1
U14D
88
DE2750
U14D
88
DE2750
ATEST
P1
3
XTAL1
T1
3
XTAL2
T14
TCK
B10
TMS
C10
TRST
D10
TDI
A11
TDO
B11
TEST
C
8
SDA
B9
SCL
C9
EXT_IN
A10
RESETZ
A9
Y
3
00
20MHz/20PPM
R7
6
4
.7
K
R7
6
4
.7
K
R9
4
4
.7
K
R9
4
4
.7
K
FB1
3
220/500mA
FB1
3
220/500mA
R117
100
R117
100
BERG-PIN2
BERG-PIN2
C
415
N
C
/100pF/
50V/
NP0
C
415
N
C
/100pF/
50V/
NP0
MAIN BOARD ASSY (12/15)
(BDP-LX55/YXCN5, BDP-LX55/VXCN5 : 08-BDLX55-MA0/Y)
(BDP-LX55/FWLXCN :
08-BDLX55-MA0/F)
(BDP-53FD/UCXCN :
08-BDLX55-MA0/U)
A
12/15
Содержание BDP-53FD
Страница 82: ...82 BDP LX55 1 2 3 4 A B C D E F 1 2 3 4 A MAIN BOARD ASSY A XP1 XP8 SIDE B ...
Страница 83: ...83 BDP LX55 5 6 7 8 5 6 7 8 A B C D E F A CON3 XP6 XP1 XP10 XP5 XP7 SIDE B ...
Страница 85: ...85 BDP LX55 5 6 7 8 5 6 7 8 A B C D E F B XP8 XS135 A XP6 XS221 A XS135 XS221 SIDE B SIDE A ...