10
Pulse Input
The trigger generator or the FPGA must be capable of delivering a 3.3 V LVDS signal into
100 Ohms and with at least a pulse width of 1 µs. The internal pulse sharpener prevents
unstable trigger response.
The LVDS standard (ANSI/TIA/EIA-644-A) specifies a threshold of ±100 mV for the
LVDS receiver.
Note: It is recommended to keep the trigger pulse width within the range of 1 µs .. 100 µs.
The LDP-AV 16N45-40 has an internal short pulse sharpener included. This feature
assures a constant pulse width.
Channel Selection
This driver includes an internal multiplexer which allows to select a specific channel thus a
laser diode. For the selection of one specific laser diode see following table:
CHSEL3 CHSEL2 CHSEL1 CHSEL0 Channel / laser diode
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
Table 1: Description – How to select a specific channel / laser diode
