MV-D752-28 User’s Manual
REV: 1.0
Page 53/61
Fig. 14: Captured picture with active 10bit LFSR
Example: VHDL Code
signal REG: STD_LOGIC_VECTOR (9 downto 0);
signal DATAIN: STD_LOGIC;
SR10R: process (ICLK)
-- 10 bit LFSR
begin
if (ICLK'event and ICLK='1') then
if (RESET = '1') then
-- reset: shift register is loaded with 1
REG <= "0000000001";
else
REG <= REG(8 downto 0) & DATAIN;
end if;
end if;
end process SR10R;
DATAIN <= REG(2) xor REG(9);
LFSR_OUT <= REG;