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Rev. 1.2
15
The PLL is connected to the SMB 10 MHz input clock if the input clock is present. The presence of the input clock
is automatically detected. If there is no input clock present, the clock source to the PLL is a 10 MHz Clock
oscillator.
Each of the clocks PXI_CLK10, PXIE_CLK100, and PXIE_SYNC100 are driven with an independent buffers.
