38
7.
Circuit Diagrams and PWB Layouts
SSB: Flash ROM & Memory
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A
A
B
B
C
C
D
D
E
E
1
s
t
S
PI Fl
as
h ROM for M
a
in Control
DDR 2M x 16
b
it x 4BK
2nd
S
PI Fl
as
h ROM for U
S
B
U4402
MODEL
CHINA (/9
3
)
MX25L4005 (4M)
AP (/9
8
)
MX25L
8
005 (
8
M)
C4401 A1
C4402 B1
C440
3
B1
C4404 B2
C4405 B2
C4406 B2
C4407 B2
C440
8
B
3
C4409 B
3
C4410 B4
C4411 B4
C4412 A6
C441
3
D7
FB4401 A2
FB4402 A2
RP4401 C4
RP4402 C4
RP440
3
C4
RP4404 C4
RP4405 C2
RP4406 C2
RP4407 C2
R4401 B
3
R4402 B
3
R440
3
C2
R4404 D2
R4405 D2
R4406 D2
R4407 D2
R440
8
D2
R4409 D2
R4410 D4
R4411 D4
R441
3
B5
R4414 A5
R4415 B5
R4416 B7
R4417 B7
R441
8
D7
R4419 D7
R4420 A6
R4421 B7
U4401 C
3
U4402 A6
U440
3
D7
S
PI_FCK
S
PI_FDI
S
PI_FDO
DQM
S
1
DQM
S
0
DATA
3
MDATA[0..15]
DATA11
DATA10
DATA9
DATA
8
DATA15
DATA14
DATA1
3
DATA12
MCLK+
MCLK-
DQ
S
0
BA1
BA0
MVREF-D
DATA2
DATA1
DATA0
DATA4
DATA7
DATA6
DATA5
CKE
MDATA4
MDATA0
MDATA7
MDATA2
MDATA1
MDATA
3
MDATA6
MDATA5
MDATA10
MDATA1
3
MDATA9
MDATA11
MDATA14
MDATA15
MDATA12
MDATA
8
WEZM
M
Z
S
A
C
Z
S
A
C
WEZ
DQ
S
1
RA
S
ZM
RA
S
Z
MCLK-
256M
MCLK+
MVREF-D
UDQM
LDQM
MADR11
MADR7
MADR1
MADR10
MADR5
MADR6
MADR
3
MADR0
MADR4
MADR
8
MADR2
MADR9
MADR[0..11]
MADR[0..11]
ADR11
ADR7
ADR1
ADR10
ADR5
ADR6
ADR
3
ADR0
ADR4
ADR
8
ADR2
ADR9
S
PI_FCK
S
PI_FDI
S
PI_FDO
S
PI_CK 10
S
PI_CZ
10
S
PI_DO
10
S
PI_DI
10
DQ
S
1
10
DQ
S
0
10
BA0
10
BA1
10
MDATA[0..15]
10
CA
S
Z
10
WEZ
10
UDQM
10
RA
S
Z
10
CKE
10
LDQM
10
MADR[0..11]
10
2ND_CZ
10
S
PI_WP
10
MCLK
10
MCLKZ
10
+
3
V
3
_
S
W
DMC
DMC
DMQ
DMQ
+2V6
DMC
DMQ
+2V6
+
3
V
3
_
S
W
+
3
V
3
_
S
W
+
3
V
3
_
S
W
C4412
0.1
u
F
RP4405
47R
1
2
3
4
8
7
6
5
RP4407
47R
1
2
3
4
8
7
6
5
C4411
1N
R440
3
22R
C4407
0.1
u
F
R440
8
56R
RP4401
47R
1
2
3
4
8
7
6
5
RP4406
47R
1
2
3
4
8
7
6
5
R4411
22R
R4409
56R
C4404
0.1
u
F
U4401
HY5DU2
8
1622FTP-5
29
3
0
3
1
3
2
3
5
3
6
3
7
38
3
9
40
2
8
41
2
4
5
7
8
10
11
1
3
54
56
57
59
60
62
6
3
65
26
27
24
2
3
22
21
20
47
16
51
44
45
46
1
1
8
33
3
9
15
55
61
3
4
4
8
66
6
12
5
8
64
49
52
14
17
19
25
4
3
5
3
50
42
A0
A1
A2
A
3
A4
A5
A6
A7
A
8
A9
A10/AP
A11
DQ0
DQ1
DQ2
DQ
3
DQ4
DQ5
DQ6
DQ7
DQ
8
DQ9
DQ10
DQ11
DQ12
DQ1
3
DQ14
DQ15
BA0
BA1
C
S
RA
S
CA
S
WE
LDM
UDM
LDQ
S
UDQ
S
CKE
CLK
CLK
MVDD
MVDD
MVDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
V
SS
V
SS
V
SS
V
SS
Q
V
SS
Q
V
SS
Q
V
SS
Q
VREF
V
SS
Q
NC
NC
NC
NC
NC
NC
NC
NC
R4410
150R 1
%
RP4402
47R
1
2
3
4
8
7
6
5
R4404
22R
C4401
10U 10V
R4414
8
2R
R4421
0R
R441
3
0R(NC)
RP440
3
47R
1
2
3
4
8
7
6
5
C440
3
0.1
u
F
R4407
56R
U440
3
MX25L
8
005M2I-15G(NC)
1
2
3
4
8
7
6
5
C
S
#
S
O
W#
GND
VCC
HOLD#
S
CK
S
I
R4416
8
2R
RP4404
47R
1
2
3
4
8
7
6
5
FB4402
120R
1
2
FB4401
120R
1
2
C440
8
0.1
u
F
R4401
10K
U4402
MX25L
8
005M2I-15G
1
2
3
4
8
7
6
5
C
S
#
S
O
W#
GND
VCC
HOLD#
S
CK
S
I
R4419
10K(NC)
R4420
10K
R4402
10K
R441
8
10K(NC)
C4402
0.1
u
F
R4406
56R
R4417
8
2R
C4405
0.1
u
F
C441
3
0.1
u
F(NC)
R4415
8
2R
C4410
0.1
u
F
C4409
0.1
u
F
C4406
0.1
u
F
R4405
22R
B11
B11
I_17610_047.ep
s
0
8
040
8
715T2
8
7
8
-1
FLA
S
H ROM & MEMORY