7.
Electrical Diagrams and PWB’s
Back-End Host Processor
MPEG
DECODER
Subpicture
decoder
MPEG1/2
2
I S
ADDRESS
DATA
Interface
MEMORY interface
VIDEO
ENCODER
DECODER
AC3
LPCM
AUDIO
IRQ
PORT 0 I/O
PORT 1 I/O
Subpicture
Video
Audio
CSn
KARAOKE
USE
SDRAM CONTROLLER
SYSTEM
JTAG
PORT 2 I/O
PORT 3 I/O
PORT 4 I/O
FRONT-END
uP ST20cpu
A/V/Sub
demultiplexer
3V
3V
3V
1V3
0V
0V
0V
0V
0V
0V
0V
4V2
3V
0V3
3V
0V
0V
3V
3V
3V
3V
0V
0V
2V5
2V5
2V5
2V5
0V
0V
0V3
2V
0V
1V5
1V5
1V2
1V2
0V
0V2
0V6
0V3
0V6
0V6
0V
0V
0V
0V
0V
0V
0V
0V
0V
4V
4V
3V
2V8
3V
3V
1V4
1V4
0V
2V5
1V3
1V3
0V
0V
2V3
2V8
1V6
2V5
2V5
M10-81
M10-82
M9-83
M9-84
0V
0V
0V
0V
0V
0V
0V
0V
3V
3V
0V5
3V
M6-77
M6-78
M5-169
M7-109
M7-126
M7-125
M7-124
M7-123
M7-122
M7-121
0V3
0V3
3V
1V5
0V8
3V
1V6
0V
0V
0V
2V3
0V
EMI Bus
3V
M7-104
M7-105
M7-106
M7-107
M7-108
M7-118
M7-117
M7-116
M7-92
M10-93
M2-64
M7-91
Back-end
F912 G24
F913 C8
M5-127
V DC Vtg measured in STOP MODE
3V
M7-120
M7-119
3V
3V
3V
3V
3V
3V
3V
3V
M5-191
M5-130
F643 L25
F644 L25
F645 L25
F646 M25
F647 F16
F648 F16
F649 F16
F650 F16
F651 F16
F652 F17
F653 F17
F654 F17
F655 E17
F656 G9
F908 D14
F909 F14
F911 F24
To Diagram
M8-165
M4-131
M8-192
VDDSTC
F624 J23
F625 J23
F626 J23
F627 J23
F628 K23
F629 K23
F630 K23
F631 L23
F637 E14
F641 L25
F642 L25
1%
F604 F20
F605 G20
F606 G22
F607 G23
F608 D11
F609 D12
F610 O20
F611 O20
F612 O20
F613 O21
F614 P18
F615 P18
F616 P4
F617 E14
F621 I23
F622 J23
F623 J23
VDDSTA
*
M7-114
M7-113
M8-190
M7-101
M7-102
M7-103
M2-71
M2-69
M2-70
M2-76
M2-56
M2-62
F602 F11
F603 F12
*
OPTION
OPTION
*
STi5580
*
STi5580
OPTION
*
3635 I24
3636 I24
3638-D K23
3642 O20
3643 O21
3644 O19
3645 P20
3646 P21
3647 P13
3648 F12
3649 G24
4600 F14
4602 C8
4605 C14
4606 D14
5600 E23
5601 E22
5602 O18
5603 P18
7601 G2
F601 F20
M2-63
M2-65
*
*
3605 D12
3606 D17
3607 D17
3608 D18
3609 H23
3611 E11
3612 F12
3613 E12
3614 E17
3616-D F16
3621 F18
3622 E14
3623 E14
3624 F20
3625 F14
3626 F21
3627 G9
3628 F9
3629 F21
+2V5
1%
BLM11
OPTION
3630 G21
3631 F23
3632 G23
3633 G24
3634 I24
BLM11
M2-54
2622 O5
2623 O6
2624 O6
2625 O7
2626 O14
2627 O15
2628 O15
2629 O16
2630 O16
2631 O17
2632 O17
2633 O17
2634 P17
2635 P18
2636 P18
2637 Q19
2638 O24
3600-D C17
3604 D11
1% 13K
*
BLM11
+3V3
STi5588
+2V5
+2V5
STi5519
*
*
+1V8
VDDSTD
OPTION
P
Q
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
M9-94
M7-95
M2-45
+2V5
BARE BOARD : 3139 243 34065
Host Processor
M8-189
25
26
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
+2V5
DCU TESTLANDS
M7-97,
M10-96
*
0R
+1V8
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
M9-85
M4-86,M7-86,M10-86
M7-100
M9-80
M8-188
M5-170
M6-78,M4-78
M6-77
M10-111
SMI Bus
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
BLM11
1% 13K
M8-111,
M8-110,
M7-112,
Back-end SDRAM
M5-90
M5-89
M7-128
M7-129
1
2
3
4
5
6
7
8
9
10
11
12
13
M5-132
M9-178
M9-112
M10-110
*
*
M4-79
P
Q
2601 D14
2603 F17
2604 F18
2605 F22
2606 F22
2607 F23
2608 F23
2609 G24
2610 G24
2612 J24
2613 J24
2614 J24
2615 M24
2616 M24
2617 N24
2618 N24
2619 O4
2620 O4
2621 O5
M2-55
and Service Interface
To
F641
RES ARRAY
RES ARRAY
RES ARRAY
M5-88
M10-97
DTS
+2V5
M5-98
M4-87,M7-87,M10-87
M7-99
3625
10K
3648
2622
10K
F650
F645
100n
VDDSTD
4600
5603
33R
3633
5601
F607
100n
2608
F616
2609
22p
F913
3608
10K
3647
47R
F628
4605
100p
2603
F912
2632
100n
F643
F654
AGNDS
+3V3ST
2630
100n
F644
F653
F603
3643
22p
2617
100n
F631
0R1
3649
2623
F911
F617
33R
3634
3635
33R
F605
F609
F604
F901
10u
10u
2607
F637
2605
33R
3636
2629
100n
100n
2628
100n
F623
2627
3611
47R
+3V3ST
2637
100n
F630
F613
22p
2614
F626
VDDSTC
3606
10K
100n
2619
5600
F908
AGNDB
AGNDB
F649
2612
22p
100n
2620
2
7
22p
2618
F615
F900
5602
F909
3K9
3646
F602
4602
2638
100p
F902
560R
3609
VDDSTA
3K3
3605
F621
3638-D
4
5
2615
22p
+3V3ST
F611
47R
F601
3621
10K
F606
10K
3628
1
8
47R
3623
100R
3616-D
100R
3622
3
6
F655
3632
100R
2604
22n
F608
3K3
3626
3642
3607
10K
F652
F651
F648
F612
2626
100n
F907
F906
2625
100n
F656
2624
100n
+3V3ST
+3V3ST
22p
2601
3612
47R
F647
2635
4u7
+3V3ST
F622
2631
100n
F627
F625
3604
3K3
F624
F614
2633
100n
22p
2613
F629
3644
100R
3K9
F610
22p
2610
3645
47R
2616
22p
10K
3613
2621
100n
F903
+3V3ST
68R
3614
100R
3631
F646
F905
3624
100R
F904
3600-D
4u7
2636
VSS_7
96
VSS_8
108
VSS_9
121
VSS_PLL
123
VSS_RGB
24
VSS_YCC
31
V_REF_DAC_RGB
28
V_REF_DAC_YC
C
35
WE0n
128
WE1n
129
Y_OUT
32
3629
3K3
VD_STI25_6
149
VD_STI25_7
171
VD_STI25_8
198
VSSA_PCM
49
VSS_1
5
VSS_10
137
VSS_11
150
VSS_12
160
VSS_13
172
VSS_14
185
VSS_15
199
VSS_2
15
VSS_3
38
VSS_4
50
VSS_5
65
VSS_6
83
VDD3_3_1
4
VDD3_3_2
47
VDD3_3_3
81
VDD3_3_4
107
VDD3_3_5
136
VDD3_3_6
159
VDD3_3_7
184
VDDA_PCM
48
VDD_PLL
122
VDD_RGB
23
VDD_YCC
30
VD_STI25_1
14
VD_STI25_2
37
VD_STI25_3
64
VD_STI25_4
94
VD_STI25_5
119
RSTn
124
R_OUT
27
SCLK
51
SDCASn
77
SDCS0n
74
SDCS1n
75
SDRASn
76
SDWEn
78
SPDIF_OUT
57
TCK
113
112
TDI
TDO
111
TMS
110
TRIG_IN
202
TRIG_OUT
203
TRSTn
109
PIO-4|0
39
PIO-4|1
40
PIO-4|2
41
PIO-4|3
42
PIO-4|4
43
PIO-4|5
44
PIO-4|6
45
PIO-4|7
46
PIXCLK_27MHz
120
PWM0_HSYNCn
116
PWM1_BOOTFROMROM
115
PWM2_VSYNC
114
RAS0n_OR_CE4n
135
RAS1n_OR_HOLDREQ
138
READNOTWRITE_OR_DMAACK
130
READY
131
PIO-2|1
205
PIO-2|2
206
PIO-2|3
207
PIO-2|4
208
1
PIO-2|5
2
PIO-2|6
3
PIO-2|7
PIO-3|0
6
PIO-3|1
7
PIO-3|2
8
PIO-3|3
9
PIO-3|4
10
PIO-3|5
11
PIO-3|6
12
PIO-3|7
13
PCM_OUT0
52
186
PIO-0|0
187
PIO-0|1
PIO-0|2
188
PIO-0|3
189
PIO-0|4
190
PIO-0|5
191
PIO-0|6
192
PIO-0|7
193
194
PIO-1|0
PIO-1|1
195
PIO-1|2
196
PIO-1|3
197
PIO-1|4
200
PIO-1|5
201
PIO-2|0
204
92
DO9
93
DQML
79
DQMU
80
G_OUT
26
IRQ0
127
126
IRQ1
125
IRQ2
I_REF_DAC_RGB
29
I_REF_DAC_YCC
36
LRCLK
56
MEMCLKIN
82
MEMCLKOUT
95
22
NRSS_OUT
OEn
117
PCM_CLK
55
151
DATA9
152
DO0
84
DO1
85
DO10
97
DO11
98
DO12
99
DO13
100
DO14
101
DO15
102
DO2
86
DO3
87
DO4
88
DO5
89
DO6
90
DO7
91
DO8
DAC_PCMOUT2
DATA0
141
DATA1
142
DATA10
153
DATA11
154
DATA12
155
DATA13
156
DATA14
157
DATA15
158
DATA2
143
DATA3
144
DATA4
145
DATA5
146
DATA6
147
DATA7
148
DATA8
B_DATA
16
B_FLAG
18
B_OUT
25
B_SYNC
19
B_V4
21
B_WCLK
20
CAS0n_OR_HOLDACK
139
CAS1n_OR_DMAREQn
140
CE1n
134
CE2n
133
CE3n
132
118
CPU_RAM_CLK
CVBS_OUT
34
C_OUT
33
53
DAC_PCMOUT1
54
ADR15
177
ADR16
178
ADR17
179
ADR18
180
ADR19
181
ADR2
162
ADR20
182
ADR21
183
ADR3
163
ADR4
164
ADR5
165
ADR6
166
ADR7
167
ADR8
168
ADR9
169
B_BCLK
17
AD5
59
AD6
60
AD7
61
AD8
62
AD9
63
105
ADC_DATA
104
ADC_LRCLK
ADC_PCMCLK
106
103
ADC_SCLK
ADR1
161
ADR10
170
ADR11
173
ADR12
174
ADR13
175
ADR14
176
7601
AD0
69
AD1
68
AD10
70
AD11
71
72
AD12
73
AD13
AD2
67
AD3
66
AD4
58
2634
100n
3627
3K3
100n
F642
3630
2606
ST_CLK
PCM_CLK_ST
4606
3K3
CTS_SER
SEL_ACLK2
CE1
PCM_CeLf_FUR
PCM_LsRs_FUR
WAIT_I2C_FUR
RESETn
27M_CLK_ST
RESET_I2C
OS_BOOT
RESETn
TCK
ST_TDI
TDO
ST_TMS
ST_TRST
LRCLK_FUR
PCMOUT0
SCLK0
SCLK_FUR
PCM_LeRi_FUR
OS_BOOT
BE_BCLK
A21
SIOCLK
RAS1ND
OEND
CSL_FUR
SEL_ACLK1
SCL
SDA
SIODATA
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
C_OUT
BE_WCLK
BE_V4
BE_SYNC
B_OUT
BE_FLAG
BE_DATA
D9
D8
D7
D6
D5
D4
D3
D2
D15
D14
D13
D12
D11
D10
D1
D0
CE_ROMN
RAS0ND
CAS1ND
CAS0ND
BE1n_FUR
BE0n_FUR
A9
A8
A7
A6
A5
A4
A3
TXD_S2B
RXD_SER
TXD_SER
SERVICE
COUNTERCLOCKWISE_C
M
GPIO2
FLASH_OEN
IRQ_FUR
IRQ_I2C
G_OUT
CVBS_OUT
RWN
SCART1
SCART0
RTS_SER
P50
GPIO1
MUTE
EANF
SUR_S2B
RXD_S2B
CPR_S2B
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD13
AD12
AD11
AD10
AD1
AD0
R_OUT
VSYNC
HSYNC
WEN
RASN
DQMU
DQML
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ1
DQ0
CSN1
CASN
AD9
KOKPCMCLK
GPIO3
CLOCKWISE_CM
PCMDATA3
KOKVOCDET
TBL_POS
YC0
RSTN
Y_OUT
SPDIF
YC7
YC6
YC5
YC4
YC3
YC2
YC1
CLK
KOKSCLK
KOKLRCLK
KOKDATA
CL 26532053_030.eps
260402
Содержание SD-4.00SA CH
Страница 7: ...Directions for Use EN 7 SD 4 00SA_CH 3 3 Directions for Use There is no DFU available ...
Страница 47: ...Electrical Diagrams and PWB s 47 SD 4 00SA_CH 7 Top Side CL 26532053_035 eps 260402 ...
Страница 49: ...Electrical Diagrams and PWB s 49 SD 4 00SA_CH 7 Bottom Side CL 26532053_036 eps 260402 ...
Страница 50: ...50 SD 4 00SA_CH 7 Electrical Diagrams and PWB s Personal Notes Personal Notes ...