Philips SD-4.00SA CH, Руководство по обслуживанию

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Test Instructions Mono Board DVD-SD4.00SA_CH EN 11 SD-4.00SA_CH 5.
5. Test Instructions Mono Board DVD-SD4.00SA_CH
5.1 General
• Impedance of measuring-equipment should be > 1M
Ω
.
• Most tests have to be done by software commands.
Together with the software command you will find a Ref.#
nbr. This is the number of the diagnostic nulceus used for
this test. More detailed information can be find in the
chapter “Diagnostic Nuclei”.
• Levels: Most measurements are digital measurements.
The signal levels specification in this document are defined
as follows:
low:< 0.3V
high:> 3.0V
LOW:< 0.4V
HIGH:> 4.5V
• All the waveforms measurement carried out in these test
instruction will be base on the testpoint indicated in the
Monoboard schematic diagram in the service manual.
5.2 General Start-up Measurements
5.2.1 Supply Check:
Table 5-1 Supply check
STi 55xx uses various power supply voltages that depend on
which processor is being used
Table 5-2 Back-end processor
The module operates in power-off and power-on only. There is
no standby mode at module level. In power-off, the module
does not response to any communication or signals.
Before starting the measurement, ensure that all power supply
are connected to the monoboard via connector 1703 or 1701
and that the PC interface cable is connected to the Service
interface connector 1500 of the monoboard.
5.2.2 Reset Check:
To ensure a proper start-up of the monoboard, the back-end
reset signal RESETn is required at the STi55xx input (testpoint
F906) after power-on.
To check the reset timing, measure the RESETn (testpoint
F906) and the +3V3ST supply (testpoint F784), reset circuit
trigger signal.
Figure 5-1 Reset
Nb: The RESETn rising edge should be at least 100msec after
the +3V3ST (refer to Figure 5-1).
If the reset input does not go high then check the reset circuit
around transistor 7409.
5.2.3 Clock Check
To check the correct functioning of the STI55xx, we first have
to check the presence of all clocks.
All clocks to be measured with 0.02% tolerance.
Table 5-3 Clock check
Figure 5-2 27M_CLK
Testpoint Supply Used by
F781 +3V3 Main supply voltage
F782 +5V Main supply voltage
F783 +12V Main supply voltage
F710 +3V3SA Analog 3V3 front-end circuitry
F711 +3V3SD Digital 3V3 front-end circuitry
F785 FUR-3V3 Digital 3V3 Furore2 interface
circuitry
F784 +3V3ST Digital 3V3 back-end circuitry
F724 3V3D Digital 3V3 cicuitry
F787 FUR-1V8 Digital 1V8 Furore2 core circuitry
F786 VDDA-FUR Analog 1V8 Furore2 circuitry
F717 +5VSA Analog 5V front-end circuitry
F715 +5VSD Digital 5V front-end circuitry
F721 +5VAV Analog 5V back-end circuitry
F718 +5VD Digital 5V back-end circuitry
F727 VDDSTA Analog STi 55xx circuitry
F729 VDDSTC Core STi 55xx circuitry
F725 VDDSTD Digital STi 55xx circuitry
Back-end
Processor VDDSTA
( Analog ) VDDSTC
( Core ) VDDSTD
( Digital )
STi 5580 +2V5 +2V5 +2V5
STi 5588 +1V8 +1V8 +3V3
STi 5519 +2V5 +2V5 +2V5
Name Testpoint Frequency Waveform
384FS F042 16.9344MHz Refer to Fig 5-3
27M_CLK_ST F932 27MHz Refer to Fig 5-2
PCM_CLK_ST F885 11.2896MHz Refer to Fig 5-5
Audio_CLK F935 11.2896MHz Refer to Fig 5-5
Iguana_CLK F207 8.4672MHz Refer to Fig 5-4
ch2
ch1
ch1: dT=73.0ms V1= 65.0mV
CH1 2.00 V=
CH2 2.00 V=
MTB50.0ms- 2.92dv ch1+
1
2
T
PM3380B
CL 16532163_019.eps
290102
PM3380 B
ch1
CH1 2.00 V= MTB10.0ns ch1+
CL 26532053_062.eps
210502