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Philips SC28L92, Техническое описание

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Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)

2000 Jan 21

33

ISR—Interrupt Status Register

This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR).
If a bit in the ISR is a ‘1’ and the corresponding bit in the IMR is also a ‘1’, the INTRN output will be asserted (Low). If the corresponding bit in
the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR - the
true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H‘00’ when the DUART is reset.

ISR  INTERRUPT STATUS REGISTER

ÁÁÁÁ

Addr

ÁÁÁÁÁ

Bit 7

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

BIT 5

ÁÁÁÁÁ

BIT 4

ÁÁÁÁÁ

BIT 3

ÁÁÁÁ

BIT 2

ÁÁÁÁÁ

BIT 1

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

ISR

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INPUT

PORT

CHANGE

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

DELTA

Break B

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

RxRDY/

FFULL B

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

TxRDY B

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Counter

Ready

ÁÁÁÁ

Á

ÁÁ

Á

Á

ÁÁ

Á

ÁÁÁÁ

Delta

Break A

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

RxRDY/

FFULL A

ÁÁÁÁÁ

Á

ÁÁÁ

Á

Á

ÁÁÁ

Á

ÁÁÁÁÁ

TxRDY A

ÁÁÁÁ

ÁÁÁÁ

0x05

ÁÁÁÁÁ

ÁÁÁÁÁ

0 = not active

ÁÁÁÁÁ

ÁÁÁÁÁ

0 = not active

ÁÁÁÁ

ÁÁÁÁ

0 = not active

ÁÁÁÁÁ

ÁÁÁÁÁ

0 = not active

ÁÁÁÁÁ

ÁÁÁÁÁ

0 = not active

ÁÁÁÁ

ÁÁÁÁ

0 = not active

ÁÁÁÁÁ

ÁÁÁÁÁ

0 = not active

ÁÁÁÁÁ

ÁÁÁÁÁ

0 = not active

ÁÁÁÁ

ÁÁÁÁÁ

1 = active

ÁÁÁÁÁ

1 = active

ÁÁÁÁ

1 = active

ÁÁÁÁÁ

1 = active

ÁÁÁÁÁ

1 = active

ÁÁÁÁ

1 = active

ÁÁÁÁÁ

1 = active

ÁÁÁÁÁ

1 = active

ISR[7]—Input Port Change Status
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.

ISR[6]—Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
command.

ISR[5]—RxB Interrupt
This bit indicates that the channel B receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.

ISR[4]—TxB Interrupt
This bit indicates that the channel B transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.

ISR[3]—Counter Ready.
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.

In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.

ISR[2]—Channel A Change in Break
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.

ISR[1]—RxA Interrupt
This bit indicates that the channel A receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.

ISR[0]—TxA Interrupt
This bit indicates that the channel A transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.

IMR—Interrupt Mask Register

The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’ the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect
on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs OP3–OP7 or the reading of the ISR.

IMR  INTERRUPT MASK REGISTER

ÁÁÁÁ

ÁÁÁÁ

Addr

ÁÁÁÁÁ

ÁÁÁÁÁ

Bit 7

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 6

ÁÁÁÁ

ÁÁÁÁ

BIT 5

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 4

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 3

ÁÁÁÁ

ÁÁÁÁ

BIT 2

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 1

ÁÁÁÁÁ

ÁÁÁÁÁ

BIT 0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

IMR

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

INPUT

PORT

CHANGE

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Delta

Break B

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RxRDY/

FFULL B

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

TxRDY B

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Counter

Ready

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Delta

Break A

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

RxRDY/

FFULL A

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

TxRDY

A

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0x05

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = not

enabled

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = not

enabled

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0 = not

enabled

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = not

enabled

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = not

enabled

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0 = not

enabled

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = not

enabled

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 = not

enabled

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

1 = enabled

ÁÁÁÁÁ

ÁÁÁÁÁ

1 = enabled

ÁÁÁÁ

ÁÁÁÁ

1 = enabled

ÁÁÁÁÁ

ÁÁÁÁÁ

1 = enabled

ÁÁÁÁÁ

ÁÁÁÁÁ

1 = enabled

ÁÁÁÁ

ÁÁÁÁ

1 = enabled

ÁÁÁÁÁ

ÁÁÁÁÁ

1 = enabled

ÁÁÁÁÁ

ÁÁÁÁÁ

1 = enabled

Содержание SC28L92

Страница 1: ... SC28L92 3 3V 5 0V Dual Universal Asynchronous Receiver Transmitter DUART Product specification Supersedes data of 1999 May 07 IC19 Data Handbook 2000 Jan 21 INTEGRATED CIRCUITS ...

Страница 2: ...mitter when the receiver buffer is full Also provided on the SC28L92 are a multipurpose 7 bit input port and a multipurpose 8 bit output port These can be used as general purpose I O ports or can be assigned specific functions such as clock inputs or status interrupt outputs under program control The SC28L92 is available in two package versions a 44 pin PLCC and 44 pin plastic quad flat pack PQFP ...

Страница 3: ...ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ VCC 3 3 5V 10 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DESCRIPTION ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Tamb 40 to 85 C ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ DRAWING NUMBER ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 44 Pin Plastic Leaded Chip Carrier PLCC ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ SC28L92A1A ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ SOT187 2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 44 Pin Plastic Quad Flat Pack PQFP ÁÁÁÁ...

Страница 4: ... 25 OP4 26 OP2 27 OP0 28 TxDA 29 RxDA 30 x1 clk Pin Function 31 x2 32 RESET 33 CEN 34 IP2 35 IP6 36 IP5 37 IP4 38 VCC 39 VCC 40 A0 41 IP3 42 A1 43 IP1 44 A2 PQFP 44 34 1 11 33 23 12 22 SD00671 1 39 17 28 40 29 18 7 PLCC 6 SD00672 Pin Function 1 NC 2 A0 3 IP3 4 A1 5 IP1 6 A2 7 A3 8 IP0 9 WRN 10 RDN 11 RxDB 12 I M 13 TxDB 14 OP1 15 OP3 Pin Function 16 OP5 17 OP7 18 D1 19 D3 20 D5 21 D7 22 VSS 23 NC ...

Страница 5: ... OP4 26 OP2 27 OP0 28 TxDA 29 RxDA 30 x1 clk Pin Function 31 x2 32 RESETN 33 CEN 34 IP2 35 IACKN 36 IP5 37 IP4 38 VCC 39 VCC 40 A0 41 IP3 42 A1 43 IP1 44 A2 PQFP 44 34 1 11 33 23 12 22 SD00673 1 39 17 28 40 29 18 7 PLCC 6 SD00674 Pin Function 1 NC 2 A0 3 IP3 4 A1 5 IP1 6 A2 7 A3 8 IP0 9 R WN 10 DACKN 11 RxDB 12 I M 13 TxDB 14 OP1 15 OP3 Pin Function 16 OP5 17 OP7 18 D1 19 D3 20 D5 21 D7 22 VSS 23 ...

Страница 6: ... ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER TIMER XTAL OSC CSRA CSRB ACR CTL CHANNEL A 16 BYTE TRANSMIT FIFO TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE FIFO MRA0 1 2 CRA SRA INPUT PORT CHANGE OF STATE DETECTORS 4 OUTPUT PORT FUNCTION SELECT LOGIC OPCR TxDA RxDA IP0 IP6 OP0 OP7 VCC VSS CONTROL TIMING INTERNAL DATABUS CHANNEL B AS ABOVE IPCR ACR OPR CTU RxDB TxDB 8 7 WATCH DOG TIMER RECEIVE...

Страница 7: ...MING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER TIMER XTAL OSC CSRA CSRB ACR CTL CHANNEL A 16 BYTE TRANSMIT FIFO TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE FIFO MRA0 1 2 CRA SRA INPUT PORT CHANGE OF STATE DETECTORS 4 OUTPUT PORT FUNCTION SELECT LOGIC OPCR TxDA RxDA IP0 IP5 OP0 OP7 VCC VSS CONTROL TIMING INTERNAL DATABUS CHANNEL B AS ABOVE IPCR ACR OPR CTU RxDB TxDB 8 6 WATCH DOG TIMER RECEIVE SHIFT ...

Страница 8: ...ark condition when the transmitter is disabled idle or when operating in local loop back mode Mark is High space is Low ÁÁÁÁ ÁÁÁÁ TxDB ÁÁÁ ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Channel B Transmitter Serial Data Output The least significant bit is transmitted first This output is held in the mark condition when the transmitter is disabled idle or when operating in local ...

Страница 9: ...ÁÁÁ ÁÁÁÁ TxDA ÁÁÁ ÁÁÁ ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Channel A Transmitter Serial Data Output The least significant bit is transmitted first This output is held in the mark condition when the transmitter is disabled idle or when operating in local loop back mode Mark is High space is Low ÁÁÁÁ ÁÁÁÁ TxDB ÁÁÁ ÁÁÁ O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ...

Страница 10: ...K 2 4 1 5 V VIH Input high voltage X1 CLK 0 8 VCC 2 4 V VOL Output low voltage IOL 2 4mA 0 2 0 4 V VOH Output high voltage except OD outputs 4 IOH 400µA VCC 0 5 V IIX1PD X1 CLK input current power down VIN 0 to VCC 0 5 0 05 0 5 µA IILX1 X1 CLK input low current operating VIN 0 130 0 µA IIHX1 X1 CLK input high current operating VIN VCC 0 130 µA Input leakage current II All except input port pins VI...

Страница 11: ...Open drain output low current in off state VIN 0 0 5 µA IODH Open drain output high current in off state VIN VCC 0 5 µA Power supply current6 ICC Operating mode CMOS input levels 5 mA Power down mode CMOS input levels 1 5 0 mA NOTES 1 Parameters are valid over specified temperature and voltage range 2 All voltage measurements are referenced to ground GND For testing all inputs swing between 0 4V a...

Страница 12: ...ÁÁÁ 0ÁÁÁ ÁÁÁ 20 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ t PD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP port valid after WRN or CEN high OPR write cycle ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 40ÁÁÁÁ ÁÁÁÁ 60 ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Timing See Figure 10 ÁÁÁÁ t IR ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ INTRN or OP3 OP7 when used as interrupts negated from ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁ...

Страница 13: ...g is between 0 4 V and 0 8 VCC All time measurements are referenced at input voltages of 0 8 V and 2 0 V and output voltages of 0 8 V and 2 0 V as appropriate 3 Test conditions for outputs CL 125 pF except open drain outputs Test conditions for open drain outputs CL 125 pF constant current source 2 6mA 4 Typical values are the average values at 25 C and 5V 5 Timing is illustrated and referenced to...

Страница 14: ...Á ÁÁÁ 0ÁÁÁ ÁÁÁ 20 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁ ÁÁÁÁ t PD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OP port valid after WRN or CEN high OPR write cycle ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 50ÁÁÁÁ ÁÁÁÁ 70 ÁÁÁÁ ÁÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Interrupt Timing See Figure 10 ÁÁÁÁ t IR ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ INTRN or OP3 OP7 when used as interrupts negated from ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ...

Страница 15: ...fied temperature and voltage range 2 All voltage measurements are referenced to ground GND For testing all inputs swing between 0 4 V and 3 0 V with a transition time of 5 ns maximum For X1 CLK this swing is between 0 4 V and 0 8 VCC All time measurements are referenced at input voltages of 0 8 V and 2 0 V and output voltages of 0 8 V and 2 0 V as appropriate 3 Test conditions for outputs CL 125 p...

Страница 16: ...ystal Clock The timing block consists of a crystal oscillator a baud rate generator a programmable 16 bit counter timer and four clock selectors The crystal oscillator operates directly from a crystal connected across the X1 CLK and X2 inputs If an external clock of the appropriate frequency is available it may be connected to X1 CLK The clock serves as the basic timing reference for the Baud Rate...

Страница 17: ... has timed out will clear the counter ready bit ISR 3 and the interrupt Invoking the Set Timeout Mode On command CRx Ax will also clear the counter ready bit and stop the counter until the next character is received The counter timer is controlled with six commands Start Stop C T Read Write Counter Timer lower register and Read Write Counter Timer upper register These commands have slight differen...

Страница 18: ...er transmitted If it is found to be High the transmitter will delay the transmission of any following characters until the CTS has returned to the low state CTS going high during the serialization of a character will not affect that character The transmitter can also control the RTSN outputs OP0 or OP1 via MR2 5 When this mode of operation is set the meaning of the OP0 or OP1 signals will usually ...

Страница 19: ...IFO is executed Receiver Time out Mode In addition to the watch dog timer described in the receiver section the counter timer may be used for a similar function Its programmability of course allows much greater precision of time out intervals The time out mode uses the received data stream to control the counter Each time a received character is transferred from the shift register to the RxFIFO th...

Страница 20: ...Each time the MR registers are accessed the MR pointer increments stopping at MR2 It remains pointing to MR2 until set to 0 or 1 via the miscellaneous commands of the command register The pointer is set to 1 on reset for compatibility with previous Philips Semiconductors UART software Mode command clock select and status registers are duplicated for each channel to provide total independent operat...

Страница 21: ...4 3 ÁÁÁÁÁ ÁÁÁÁÁ Bit 2 ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Bit 1 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ RxRTS Control ÁÁÁÁÁ ÁÁÁÁÁ RxINT BIT 1 ÁÁÁÁÁ ÁÁÁÁÁ Error Mode ÁÁÁÁÁÁ ÁÁÁÁÁÁ Parity Mode ÁÁÁÁÁ ÁÁÁÁÁ Parity Type ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Bits per Character MR2 MODE REGISTER 2 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Bits 7 6 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Bit 5 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Bit 4 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bit 3 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ Channel Mode ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ...

Страница 22: ... accessed by setting the MR pointer to 0 via the command register command B ÁÁÁÁÁ Addr ÁÁÁÁÁ Bit 7 ÁÁÁÁÁ BIT 6 ÁÁÁÁÁ BITS 5 4 ÁÁÁÁÁÁ BIT 3 ÁÁÁÁÁ BIT 2 ÁÁÁÁ BIT 1 ÁÁÁÁÁÁ BIT 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ MR0A MR0B ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Rx WATCHDOG ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RxINT BIT 2 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ TxINT 1 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ FIFO SIZE ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ BAUD RATE EXTENDED II ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ TEST 2 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ...

Страница 23: ...Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 RxRDY 1 FFULL ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 0 Char 1 Block ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 00 With Parity 01 Force Parity 10 No Parity 11 Multi drop Mode ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 0 Even 1 Odd ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 00 5 01 6 10 7 11 8 NOTE In block error mode block error conditions must be cleared by using the error reset command command 4x or a receiver reset MR1A i...

Страница 24: ... bits are inactive 5 The received parity is checked but is not regenerated for transmission i e transmitted parity bit is as received 6 Character framing is checked but the stop bits are retransmitted as received 7 A received break is echoed as received until the next valid start bit is detected 8 CPU to receiver communication continues normally but the CPU to transmitter link is disabled MR2A 7 6...

Страница 25: ...rements of 1 16 bit In all cases the receiver only checks for a mark condition at the center of the stop bit position one half bit time after the last data bit or after the parity bit if enabled is sampled If an external 1X clock is used for the transmitter then MR2A 3 0 selects one stop bit and MR2A 3 1 selects two stop bits to be transmitted MR0B Channel B Mode Register 0 MR0B is accessed when t...

Страница 26: ...K ÁÁÁÁÁÁ ÁÁÁÁÁÁ 57 6K ÁÁÁÁÁÁ ÁÁÁÁÁÁ 57 6K ÁÁÁÁÁ ÁÁÁÁÁ 1001 ÁÁÁÁÁ ÁÁÁÁÁ 4 800 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4 800 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 28 8K ÁÁÁÁÁÁ ÁÁÁÁÁÁ 28 8K ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4 800 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4 800 ÁÁÁÁÁ 1010 ÁÁÁÁÁ 7 200 ÁÁÁÁÁÁ 1 800 ÁÁÁÁÁÁ 7 200 ÁÁÁÁÁÁ 1 800 ÁÁÁÁÁÁ 57 6K ÁÁÁÁÁÁ 14 4K ÁÁÁÁÁ ÁÁÁÁÁ 1011 ÁÁÁÁÁ ÁÁÁÁÁ 9 600 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 9 600 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 57 6K ÁÁÁÁÁÁ ÁÁÁÁÁÁ 57 6K ÁÁÁÁÁÁ ÁÁÁÁÁÁ 9 600 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 9 600 ...

Страница 27: ... 300 ÁÁÁÁÁÁÁÁÁÁÁ 4 8 ÁÁÁÁÁÁÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ 600 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 9 6 ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ 1050 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 16 756 ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ 0 260 ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ 1200 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 19 2 ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ 1800 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 28 8 ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ 0...

Страница 28: ...nsmitter is active the break begins when transmission of the character is completed If a character is in the TxFIFO the start of the break will be delayed until that character or any other loaded subsequently are transmitted The transmitter must be enabled for this command to be accepted 0111 Stop break The TxDA line will go High marking within two bit times TxDA will remain High for one bit time ...

Страница 29: ...y can detect breaks that originate in the middle of a received character However if a break begins in the middle of a character it must persist until at least the end of the next character time in order for it to be detected This bit is reset by command 4 0100 written to the command register or by receiver reset SRA 6 Channel A Framing Error This bit when set indicates that a stop bit was not dete...

Страница 30: ...n drain output Note that this output is not masked by the contents of the IMR OPCR 5 OP5 Output Select This bit programs the OP5 output to provide one of the following 0 The complement of OPR 5 1 The Channel B receiver interrupt output which is the complement of ISR 5 When in this mode OP5 acts as an open drain output Note that this output is not masked by the contents of the IMR OPCR 4 OP4 Output...

Страница 31: ...he OPR bit configuration ÁÁÁÁ ÁÁÁÁ Addr ÁÁÁÁÁ ÁÁÁÁÁ Bit 7 ÁÁÁÁÁ ÁÁÁÁÁ BIT 6 ÁÁÁÁÁ ÁÁÁÁÁ BIT 5 ÁÁÁÁ ÁÁÁÁ BIT 4 ÁÁÁÁÁ ÁÁÁÁÁ BIT 3 ÁÁÁÁÁ ÁÁÁÁÁ BIT 2 ÁÁÁÁÁ ÁÁÁÁÁ BIT 1 ÁÁÁÁ ÁÁÁÁ BIT 0 ÁÁÁÁ ÁÁÁÁ ROPR ÁÁÁÁÁ ÁÁÁÁÁ OP 7 ÁÁÁÁÁ ÁÁÁÁÁ OP 6 ÁÁÁÁÁ ÁÁÁÁÁ OP 5 ÁÁÁÁ ÁÁÁÁ OP 4 ÁÁÁÁÁ ÁÁÁÁÁ OP 3 ÁÁÁÁÁ ÁÁÁÁÁ OP 2 ÁÁÁÁÁ ÁÁÁÁÁ OP 1 ÁÁÁÁ ÁÁÁÁ OP 0 ÁÁÁÁ ÁÁÁÁ 0x0F ÁÁÁÁÁ ÁÁÁÁÁ 1 reset bitÁÁÁÁÁ ÁÁÁÁÁ 1 reset bit ÁÁÁÁÁ ÁÁÁÁÁ...

Страница 32: ...6 4 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ MODE ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ CLOCK SOURCE ÁÁÁ ÁÁÁ 000 ÁÁÁÁ ÁÁÁÁ Counter ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ External IP2 ÁÁÁ ÁÁÁ 001 ÁÁÁÁ ÁÁÁÁ Counter ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ TxCA 1X clock of Channel A transmitter ÁÁÁ 010 ÁÁÁÁ Counter ÁÁÁÁÁÁÁÁÁÁÁÁ TxCB 1X clock of Channel B transmitter ÁÁÁ ÁÁÁ ÁÁÁ 011 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Counter ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Crystal o...

Страница 33: ...upt level programmed in the MR0 5 4 bits This bit has a different meaning than the Tx RDY bit in the status register ISR 3 Counter Ready In the counter mode this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command In the timer mode this bit is set once each cycle of the generated square wave every other time that the counter timer r...

Страница 34: ... value in CTPU and CTPL is changed the current half period will not be affected but subsequent half periods will be affected The counter ready status bit ISR 3 is set once each cycle of the square wave The bit is reset by a stop counter command read with A3 A0 H F The command however does not stop the C T The generated square wave is output on OP3 if it is programmed to be the C T output In the co...

Страница 35: ... It is usually the RTS output of the receiver that will be connected to the transmitter s CTS input The receiver will set RTS high when the receiver FIFO is full AND the start bit of the ninth or 17th character is sensed Transmission then stops with nine or 17 valid characters in the receiver When MR2 4 is set to one CTSN must be at zero for the transmitter to operate If MR2 4 is set to zero the I...

Страница 36: ...DF tDAT tDAH tCH tRWD tDD tDCR tAH DATA VALID NOT VALID tDA NOTE DACKN low requires two rising edges of X1 clock after CSN is low SD00687 Figure 6 Bus Timing Read Cycle 68XXX mode X1 CLK A1 A4 RWN CSN D0 D7 DTACKN tCSC tAS tCS tDH tDAT tDAH tCH tRWD tDS tDCW tAH NOTE DACKN low requires two rising edges of X1 clock after CSN is low SD00688 Figure 7 Bus Timing Write Cycle 68XXX mode ...

Страница 37: ...T 2000 Jan 21 37 X1 CLK INTRN IACKN D0 D7 DTACKN tCSC tDD tDF tCSD tDAL tDCR tDAH tDAT NOTE DACKN low requires two rising edges of X1 clock after CSN is low SD00149 Figure 8 Interrupt Cycle Timing 68XXX mode b OUTPUT PINS RDN IP0 IP6 WRN OP0 OP7 tPS tPH tPD OLD DATA NEW DATA a INPUT PINS SD00135 Figure 9 Port Timing ...

Страница 38: ...ent are pronounced and can greatly affect the resultant measurement VM VOL 0 5V VOL WRN INTERRUPT1 OUTPUT tIR VM VOL 0 5V VOL RDN INTERRUPT1 OUTPUT tIR SD00136 Figure 10 Interrupt Timing 80xxx mode C1 C2 24pF FOR CL 20pF tCLK tCTC tRx tTx X1 CLK CTCLK RxC TxC tCLK tCTC tRx tTx VCC 470Ω X1 X2 CLK NOTE X2 MUST BE LEFT OPEN X2 3 6864MHz X1 C1 C2 SC28L92 NOTE RESISTOR REQUIRED FOR TTL INPUT TO UART CI...

Страница 39: ...OUTPUT SD00138 Figure 12 Transmitter External Clocks tRXS tRXH RxC 1X INPUT RxD SD00139 Figure 13 Receiver External Clock TRANSMITTER ENABLED TxD D1 D2 D3 D4 D6 BREAK TxRDY SR2 WRN D1 D8 D9 D10 D12 START BREAK STOP BREAK D11 WILL NOT BE WRITTEN TO THE TxFIFO CTSN1 IP0 RTSN2 OP0 OPR 0 1 OPR 0 1 NOTES 1 Timing shown for MR2 4 1 2 Timing shown for MR2 5 1 SD00155 Figure 14 Transmitter Timing ...

Страница 40: ... DATA D10 D11 WILL BE LOST DUE TO OVERRUN OVERRUN SR4 RESET BY COMMAND RTS1 OP0 OPR 0 1 NOTES 1 Timing shown for MR1 7 1 2 Shown for OPCR 4 1 and MR 6 0 SD00156 Figure 15 Receiver Timing TRANSMITTER ENABLED TxD ADD 1 TxRDY SR2 WRN MR1 4 3 11 MR1 2 1 1 BIT 9 D0 0 BIT 9 ADD 2 1 BIT 9 MASTER STATION ADD 1 MR1 2 0 D0 MR1 2 1 ADD 2 RxD ADD 1 1 BIT 9 D0 0 BIT 9 ADD 2 1 BIT 9 PERIPHERAL STATION 0 BIT 9 0...

Страница 41: ...V 5 0V Dual Universal Asynchronous Receiver Transmitter DUART 2000 Jan 21 41 INTRN DACKN D0 D7 TxDA B OP0 OP7 125pF 5V I 2 4mA 125pF I 2 4mA VOL return to VCC for a 0 level I 400µA VOH return to VSS for a 1 level SD00690 Figure 17 Test Conditions on Outputs ...

Страница 42: ...Philips Semiconductors Product specification SC28L92 3 3V 5 0V Dual Universal Asynchronous Receiver Transmitter DUART 2000 Jan 21 42 PLCC44 plastic leaded chip carrier 44 leads SOT187 2 ...

Страница 43: ...iconductors Product specification SC28L92 3 3V 5 0V Dual Universal Asynchronous Receiver Transmitter DUART 2000 Jan 21 43 QFP44 plastic quad flat package 44 leads lead length 1 3 mm body 10 x 10 x 1 75 mm SOT307 2 ...

Страница 44: ...lication Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright ...

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