Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
16
Block Diagram
The SC28L92 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to the Block Diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus.
Interrupt Control
A single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all currently
active interrupting conditions. Outputs OP3–OP7 can be
programmed to provide discrete interrupt outputs for the transmitter,
receivers, and counter/timer. When OP3 to OP7 are programmed as
interrupts, their output buffers are changed to the open drain active
low configuration. The OP pins may be used for DMA and modem
control as well. (See output port notes).
FIFO Configuration
Each receiver and transmitter has a 16 byte FIFO. These FIFOs
may be configured to operate at a fill capacity of either 8 or 16 bytes.
This feature may be used if it is desired to operate the 28L92 in strict
compliance with the 26C92. The 8 byte/16 byte mode is controlled
by the MR0[3] bit. A 0 value for this bit sets the 8 bit mode ( the
default); a 1 sets the 16 byte mode.
The FIFO fill interrupt level automatically follow the programming of
the MR0[3] bit. See Tables 3 and 4.
68XXX mode
When the I/M pin is connected to V
CC
(ground), the operation of the
SC28L92 switches to the bus interface compatible with the Motorola
bus interfaces. Several of the pins change their function as follows:
Ip6 becomes IACKN input
RDN becomes DACKN
WRN becomes R/WN
The interrupt vector is enabled and the interrupt vector will be placed
on the data bus when IACKN is asserted low. The interrupt vector
register is located at address 0xC. The contents of this register are
set to 0x0F on the application of RESETN.
The generation of DACKN uses two positive edges of the X1 clock
as the DACKN delay from the falling edge of CEN. If the CEN is
withdrawn before two edges of the X1 clock occur, the
generation of DACKN is terminated. Systems not strictly requiring
DACKN may use the 68XXX mode with the bus timing of the 80XXX
mode greatly decreasing the bus cycle time.
TIMING CIRCUITS
Crystal Clock
The timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the Baud
Rate Generator (BRG), the counter/timer, and other internal circuits.
A clock signal within the limits specified in the specifications section
of this data sheet must always be supplied to the DUART. If an
external clock is used instead of a crystal, X1 should be driven using
a configuration similar to the one in Figure 11. Nominal crystal rate is
3.6864 MHz. Rates up to 8 MHz may be used.
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 28 commonly used data
communications baud rates ranging from 50 to 38.4K baud.
Programming bit 0 of MR0 to a “1” gives additional baud rates of
57.6kB, 115.2kB and 230.4kB (531kHz with X1 at 8.5MHz). These
will be in the 16X mode. A 3.6864 MHz crystal or external clock
must be used to get the standard baud rates. The clock outputs from
the BRG are at 16X the actual baud rate. The counter/timer can be
used as a timer to produce a 16X clock for any other baud rate by
counting down the crystal clock or an external clock. The four clock
selectors allow the independent selection, for each receiver and
transmitter, of any of these baud rates or external timing signal.
Counter/Timer
The counter timer is a 16–bit programmable divider that operates in
one of three modes: counter, timer, time out. In the timer mode it
generates a square wave. In the counter mode it generates a time
delay. In the time out mode it monitors the time between received
characters. The C/T uses the numbers loaded into the
Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper
Register (CTUR) as its divisor.
The counter/timer clock source and mode of operation (counter or
timer) is selected by the Auxiliary Control Register bits 6 to 4
(ACR[6:4]). The output of the counter/timer may be used for a baud
rate and/or may be output to the OP pins for some external function
that may be totally unrelated to data transmission. The
counter/timer also sets the counter/timer ready bit in the Interrupt
Status Register (ISR) when its output transitions from 1 to 0. A
register read address (see Table 1) is reserved to issue a start
counter/timer command and a second register read address is
reserved to issue a stop command. The value of D(7:0) is ignored.
The START command always loads the contents of CTUR, CTLR to
the counting registers. The STOP command always resets the ISR
(3) bit in the interrupt status register.
Timer Mode
In the timer mode a symmetrical square wave is generated whose
half period is equal in time to division of the selected counter/timer
clock frequency by the 16–bit number loaded in the CTLR CTUR.
Thus, the frequency of the counter/timer output will be equal to the
counter/timer clock frequency divided by twice the value of the
CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be
set each time the counter/timer transitions from 1 to 0. (High to low)
