Circuit Diagrams and PWB Layouts
10.
10-1-20
B, DDR I/O SUPPLY MTK 1
19580_101_140313.eps
14-03-26
DDR I/O SUPPLY MTK 1
B
B
2014-02-14
1
715RLPCB000000037
MTK UHD 50 Hz
7800
50V 22pF
C038U
RES
50V
1nF
C043U
22uF
C050U
6,3V
16V
100nF
C059U
+12V
16V
10uF
C065U
C066U
10uF
16V
+1V5-MTK
470K
R043U
RES
C060U
100nF
16V
C051U
22uF
6,3V
6,3V
22uF
C052U
RES
4
5
10
R040U
3
6
10
R040U
2
7
10
R040U
1
8
10
R040U
C044U
1nF
50V
50V
1nF
C045U
1%
22K
R037U
GND-D1
X010U
I022U
I023U
I024U
I025U
F006U
I026U
30H
L006U
I027U
I028U
F007U
1.5uH
L002U
+1V5-MTK
50V 22pF
C039U
RES
+3V3
1%
22K
R038U
I029U
4
5
R041U
10
3
6
R041U
10
2
7
R041U
10
1
8
R041U
10
50V
1nF
C046U
C047U
1nF
50V
I030U
6,3V
C053U
22uF
6,3V
22uF
C054U
RES
C055U
22uF
6,3V
F008U
+3V3
C061U
100nF
16V
I031U
I032U
C067U
10uF
16V
C062U
100nF
16V
R039U
1%
22K
GND-D1
GND-D1
R048U
1%
68K
GND-D1
GND-D1
GND-D1
L003U
2,2uH
RES
RES
VIN1
VBST1
SW1
PGND1
EN1
PG1
VFB1
VIN2
VBST2
SW2
PGND2
EN2
PG2
VFB2
VREG5
GND_HS
GND
U011U
8
17
9
10
11
12
13
14
15
16
7
6
5
4
3
2
1
TPS54494PWP
GND-D1
1V5+3V3
1V5+3V3
U013U
11
8
4
9
6
5
3
10
7
2
1
REFIN
VLDO_IN
EN
VIN
VO
VOSNS
REFOUT
PGOOD
PGND
GND
GND_HS
TPS51200DRC
R051U
10K
C073U
10uF
6,3V
C079U
100nF
16V
+1V5-MTK
10K
R052U
6,3V
10uF
C074U
+1V5-MTK
+3V3
+3V3
6,3V
10uF
C075U
C076U
10uF
6,3V
6,3V
10uF
C077U
+VTT
VTT-REF
C078U
1nF
50V
+3V3
+3V3-A
L007U
30H
F037U
C070U
1uF
16V
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
I051U
F041U
F042U
+5V
D001U
RED
R067U
1K
6,3V
10uF
C096U
3V3-OK
C082U
100uF
16V
RES
R035U
270K