Circuit Descriptions, Abbreviation List, and IC Data Sheets
8
9.
9.2
Front-End
Refer to figure “9-1 Architecture of TV522 platform” earlier in
this chapter for details. Refer also to block diagrams B03A,
B03B and B03C.
9.2.1
Device specifications
Tuner (TD1716)
The tuner has the following specifications:
•
Hybrid tuner with symmetrical IF output.
•
Down conversion from RF to IF frequency (picture carrier
39.875 MHz at analogue reception, centre frequency
36.166 MHz at digital reception).
•
AGC control signal is coming from master IF device
(TDA9898).
•
Only 5 V external supply needed (internal DC-DC
conversion to 3.3 V).
•
4 MHz output is used by channel decoder (TDA10048) and
master IF device (TDA9898).
The application in this chassis is as follows:
•
I
2
C address C0.
•
Broadband AGC, no IF section.
•
I
2
C communication buffered via MUX.
•
Gain to obtain optimised Master IF input level; AGC control
is completely inside the tuner.
•
Output level ca. 110 dB
μ
V (for strong input signal).
Repair tip:
after replacement of the tuner, the option code
should be checked, even when the set appears to function
correctly! Refer also to chapter 5 “Service Modes, Error Codes,
and Fault Finding”.
Master IF (TDA9898)
•
Down conversion from IF to low-IF frequency.
•
Down conversion from IF to SIF.
•
CVBS output.
The application in this chassis is as follows:
•
I
2
C address 0x86.
•
Down conversion from IF to low-IF frequency (5.166 MHz
centre frequency).
•
Advanced filtering (for further rejection of adjacent
channels).
•
Gain to obtain optimised channel decoder level. Control
signal is coming from channel decoder.
SAW filter
X6874D and X3451K
•
Analogue sound for BG, I, DK, L, L’.
•
DVB-T (digital reception sound
and
video).
For digital reception, the application in this chassis is as
follows:
•
Rejection of adjacent channels.
•
Switching is done by Master IF (3 inputs).
•
One SAW covering both 7 and 8 MHz channels.
X6774D
•
Analogue video for BG, I, DK, L, L’.
Channel decoder (TDA10048) DVB-T
The channel decoder has the following specifications:
•
I
2
C address 0x10.
•
Decoding from low-IF to MPEG transport stream.
•
During decoding: de-modulation, de-interleaving and error
correction.
•
External clock buffer required.
•
No start-up requirements.
•
AGC monitor.
Channel decoder (TDA10023) DVB-C
The channel decoder has the following specifications:
•
I
2
C address 0x1C.
•
Decoding from low-IF to MPEG transport stream.
•
During decoding: de-modulation, de-interleaving and error
correction.
•
External clock buffer required.
•
No start-up requirements.
•
AGC monitor.
9.2.2
Digital signal processing (front-end)
Refer to figure “9-4 DVB-C signal broadcast reception block
diagram” and “9-5 DVB-T signal broadcast reception block
diagram” for details of digital signal processing.
Содержание ME8
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Страница 37: ...Service Modes Error Codes and Fault Finding EN 37 Q522 1E LA 5 Personal Notes E_06532_012 eps 131004 ...
Страница 38: ...Service Modes Error Codes and Fault Finding EN 38 Q522 1E LA 5 ...
