Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.
9.11.3
Diagram A12, Type SiI9993CT (IC7808)
Figure 9-7 Internal Block Diagram and Pin Configuration
DAC
V
CC
1
100-Pin
TQFP
(Top
V
ie
w
)
N
/C
2
DACG
N
D
3
N
/C
4
DACG
N
DR
5
DAC
V
CCR
6
AnRPr
7
COMP
8
RSET
9
DACG
N
DG
10
DAC
V
CCG
11
AnGY
12
DACG
N
DB
13
DAC
V
CCB
14
AnBP
b
15
G
N
D
16
V
CC
17
RS
V
DL
1
8
RS
V
DO
19
RS
V
DO
20
O
V
CC
21
PG
N
D2
22
P
V
CC2
23
PLLI
N
24
N
/C
25
MC
L
K
O
U
T
26
MC
L
K
I
N
27
OG
N
D
2
8
SP
D
IF
29
SD
O
30
W
S
31
SC
K
32
HS
Y
N
C
33
V
SY
N
C
34
DE
35
Q2
3
36
Q2
2
37
Q2
1
3
8
Q2
0
39
V
CC
40
G
N
D
41
Q1
9
42
Q1
8
43
Q1
7
44
OG
N
D
45
OD
C
K
46
O
V
CC
47
Q1
6
4
8
Q1
5
49
Q1
4
50
75
Q1
74
O
V
CC
73
CSDA
72
Q3
71
Q4
70
Q5
69
Q6
6
8
Q7
67
Q
8
66
OG
N
D
65
O
V
CC
64
Q9
63
Q10
62
Q11
61
Q12
60
Q13
59
5
8
57
56
55
54
53
52
51
Q0
V
CC
100
G
N
D
99
AG
N
D9
8
R
X
2+
97
R
X
2-
96
A
V
CC
9
5
AG
N
D9
4
A
V
CC
9
3
R
X
1+
92
RX
1
-
91
AG
N
D
90
A
V
CC
8
9
AG
N
D
88
RX
0
+
8
7
RX
0
-
8
6
AG
N
D
8
5
RX
C+
8
4
RX
C-
8
3
A
V
CC
8
2
EX
T
_
R
E
S
8
1
P
V
CC1
8
0
PG
N
D1
79
OG
N
D7
8
DS
CL
77
DS
DA
76
CSCL
RS
V
DL
Q2
RESET#
I
N
T
OG
N
D
V
CC
G
N
D
SiI 9993
BLOCK DIAGRAM
PIN CONFIGURATION
E_14620_149.eps
090
8
04
HDCP
Decryption
Engine
HDCP
Keys
EEPROM
Registers
----------------
Config
u
ration
Logic Block
XOR
Mask
V
ideo
Color
Space
Con
v
erter
Up/Do
w
n
Sampling
control
signals
I
2
C
Sla
v
e
24
DE
Q[23:0]
DSDA
DSCL
R_EXT
RXC±
RX0±
RX1±
RX2±
I
N
T
RESET#
A
u
dio
Data
Decode
Logic
Block
SPDIF
MCLKOUT
PanelLink
TMDS
TM
Digital
Core
MCLK
Gen
HSY
N
C
V
SY
N
C
ODCK
SD0
SCK
W
S
MCLKI
N
Mode
Control
A
u
x Data
Logic
Block
control
signals
V
ideo
DAC
30
AnGY
AnRPr
AnBP
b
I
2
C
Sla
v
e
CSDA
CSCL
OMPC
SETR