7.
Circuit Diagrams and PWB Layouts
Double Window Panel V-Chip Processor
V CHIP PROCESSOR
##
F3-22
SEL
H SEL
XOUT
SEN
HIN/XIN
SMS
VIDEO
CSYNC
LPF
RREF
VSS
VDD
VIN
SDA
SCK
SDO
NC
NC
1
2
3
4
1
2
3
4
A
B
C
A
B
C
1501 B1
2501 A1
2502 B1
2503 B1
2504 C1
2505 C1
2506 B3
2507 A4
2508 C1
2509 C1
2511 B4
3501 A2
3502 A1
3503 B1
3504 C1
3506 B3
3507 A4
3508 B1
3509 A3
3510 A3
5501 B3
7501 A2
100R
3510
100R
3509
32K768
1501
DT-38
56p
2505
1u
2507
6K8
3507
6u8
5501
2511
100n
100n
2506
10K
3506
6n8
2508
68n
2504
6K8
3504
100n
2509
100n
2503
470R
3503
8p2
2502
22p
2501
3508
10M
10M
3502
9
470K
3501
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
+5VD
SCL
SDA
PIP_CVBS_OUT
Z86130
7501
1
10
C5
C5
3139 123 5952.1
E_14600_077.eps
171204
Double Window Panel NV ROM
SCL
ADR
0
1
2
SDA
WC
B
2512 A2
3512 B2
3513 B2
7502 A1
NV ROM
1
2
3
1
2
3
A
B
A
1
2
3
6
5
4
7
7502
M24C32-WMN6T
EEPROM
Φ
(4Kx8)
3139 123 5952.1
2512
100n
3513
100R
SDA
SCL
+5VS
100R
3512
C6
C6
E_14600_081.eps
171204
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