Philips CEM5000/00, Руководство по обслуживанию

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TDA7703/TDA7703R
- a chip address byte must be sent at the beginning of the transmission. The value can be C2 or C8
(according to the mode chosen at start-up during boot) for “write”;
- as many data bytes as one wants can follow the address before the communication is terminated.
See the next section for details on the frame format;
- STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the transmission.
Red lines represent transmissions from the TDA7703 to the uP.
A “read” communication example is shown in the figure below, for an unspecified number of data bytes (see
later on for frame structure decription):
SDA
a7 a6 … a0 d7 d6 … d0
SCL
clk1 clk2 … clk8 clk9 clk1 clk2 … clk8 clk9
START
address
ACK
data
ACK STOP
Figure 4
I
2
C “read” sequence
The sequence is very similar to the “write” one and has the same constraints for start, stop, data latching.
The differences follow:
- a chip address must always be sent by the uP to the TDA7703; the address must be C3 (if C2 had
been selected at boot) or C9 (if C8 had been selected at boot);
- a header is transmitted after the chip address (the same happens for “write”) before data are
transferred from the TDA7703 to the uP. See the next section for details on the frame format;
- when data are transmitted from the TDA7703 to the uP, the uP keeps the SDA line H;
- the ACKnowledge pulse is generated by the uP for those data bytes that are sent by the TDA7703 to
the uP. Failure of the uP to generate an ACK pulse on the 9
th
CLK pulse has the same effect on the
TDA7703 as a STOP.
The max. clock speed is 500kbits/s.
Rev. 1.0 7/22