Philips CEM5000/00, Руководство по обслуживанию

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TDA7703/TDA7703R
5.12 I
2
C ADDRESS SELECTION / RDS INTERRUPT INTERFACE PIN
As explained also in 5.13.1, there is one pin (RDSINT, pin 29) dedicated to selecting the I
2
C
address of the device. In the TDA7703R only this pin serves the additional function of RDS
interrupt output to communicate to the uP when a new RDS block is available. This pin is voltage-
tolerant up to 3.5V and can drive currents up to 0.5mA.
5.13 SERIAL INTERFACE
The device is controlled with a standard I
2
C bus interface.
Through the serial bus, the processing parameters can be modifed and the signal quality
parameters and the RDS information (TDA7703R only) can be read out.
The operation of the device is handled through high level commands sent by the main car-radio uP
through the serial interface, which allow to simplify the operations carried out in the main uP. The
high level commands include among others:
- set frequency (which allows to avoid computing the PLL divider factors);
- start seek (the seek operation can be carried out by the TDA7703/TDA7703R) in a completely
autonomous fashion);
- RDS seek/search (jumps to AF and quality measurements are automatically sequenced)
(TDA7703R only).
5.13.1 I
2
C BUS ADDRESS MODE CHOICE
The device can communicate with the main uP via I
2
C, with two possible different addresses. The
configuration is chosen by setting the proper value (0V or V
DD
) at pin 29 and it is latched (e.g. made
effective) when the RSTN line transitions from low to high (when RSTN is low, the IC is in reset
mode).
The voltage level forced to pin 29 must be released to start the system operation a suitable time
after the RSTN line has gone high.
If pin 29 is kept low when RSTN rises, the I
2
C address is 0xC2(w)/0xC3(r).
If pin 29 is kept high when RSTN rises, the I
2
C address is 0xC8(w)/0xC9(r).
The status of pin 29 during the reset phase can be set to:
high
, through an external <10 kohm resistor tied to 3.3V (pin 25), or
low
, by not forcing any voltage on it from outside, as a 50 kohm internal pull-down resistor is present.
To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the RSTN line low until
the IC supply pins have reached their steady state, and then an additional time Treset (see section 6.9).
5.13.2 I
2
C BUS PROTOCOL
The I
2
C protocol requires two signals: clock (SCL) and data (SDA – bidirectional). The protocol requires an
acknowledge after any 8 bit transmission.
A “write” communication example is shown in the figure below, for an unspecified number of data bytes (see
Communication Protocol Manual for frame structure decription):
d7 d6
ACK ACK
data
STOP
clk1 clk2 … clk8 clk9 clk1 clk2
START
address
a0 … d0
… clk8 clk9
a7 a6 …
SCL
SDA
Figure 3
I
2
C “write” sequence
The sequence is made of the following phases:
- START: SDA line transitioning from H to L with SCL H. This signifies a new transmission is starting;
- data latching: on the rising SCL edge. The SDA line can transition only when SCL is low (otherwise
its transitions are interpreted as either a START or a STOP transition);
- ACKnowledge: on the 9
th
SCL pulse the uP keeps the SDA line H, and the TDA7703 pulls it down if
communication has been successful. Lack of the acknowledge pulse generation from the TDA7703
means that the communication has failed;
Rev. 1.0 6/22