9-2-31 NT334e_DDR
C5299
1
0
0N
F
1
6V
R7581
0R05 1/16W
TP7559
R7594
NC/1K 1/16W 1%
TP7558
C5281
1N 50V
R7580
1K 1%
TP7554
R7592
0R05 1/16W
R7590
NC/1K 1/16W 1%
TP7560
NT72334TBG/BA
U5000A
A_VREFCA
R1
A_VREFDQ
R2
A_ZQ
T1
B_VREFCA
AB1
B_VREFDQ
AB2
B_ZQ
AC1
MLDO_OUT
AC2
C_DQSLP
AJ7
C_DQSLN
AK8
C_DQL0
AL5
C_DQL1
AJ11
C_DQL2
AM5
C_DQL3
AK12
C_DQL4
AK4
C_DQL5
AM13
C_DQL6
AJ4
C_DQL7
AJ12
C_DML
AK11
C_DQSUP
AM9
C_DQSUN
AL9
C_DQU0
AJ10
C_DQU1
AJ6
C_DQU2
AM11
C_DQU3
AK6
C_DQU4
AJ9
C_DQU5
AM7
C_DQU6
AK10
C_DQU7
AL7
C_DMU
AJ5
D_DQSLP
AJ19
D_DQSLN
AK20
D_DQL0
AL17
D_DQL1
AJ23
D_DQL2
AM17
D_DQL3
AK24
D_DQL4
AK16
D_DQL5
AM25
D_DQL6
AJ16
D_DQL7
AJ24
D_DML
AK23
D_DQSUP
AM21
D_DQSUN
AL21
D_DQU0
AJ22
D_DQU1
AJ18
D_DQU2
AM23
D_DQU3
AK18
D_DQU4
AJ21
D_DQU5
AM19
D_DQU6
AK22
D_DQU7
AL19
D_DMU
AJ17
S_CLKP
AJ14
S_CLKN
AK14
S_A0
AG19
S_A1
AH16
S_A2
AG21
S_A3
AG24
S_A4
AG15
S_A5
AH24
S_A6
AF16
S_A7
AH22
S_A8
AG16
S_A9
AH19
S_A10
AG13
S_A11
AH18
S_A12
AH15
S_A13
AH21
S_A14
AF15
S_A15
AF14
S_BA0
AG22
S_BA1
AH13
S_BA2
AF22
S_CASN
AG18
S_RASN
AF19
S_WEN
AF18
S_RESETN
AF21
C_CSN
AL3
D_CSN
AK15
S_ODT
AF24
S_CKE
AF13
SLDO_OUT
AJ25
C5283
100N 16V
C5278
1
0
0N
F
1
6V
TP7550
C5289
N
C
/1
0
0
N
F
1
6
V
R7586
1K 1%
TP7561
R7610
0 OHM 1/8W
C5293
1
0
0N
F
1
6V
C5277
1
0
0N
F
1
6V
R7574
1K 1%
TP7552
C5229
1N 50V
TP7557
R7593
240R 1%
C5286
2
2
U
F
6
.3
V
R7583
1K 1%
DDR3 DRAM
U5005
W631GG6MB-12
V
D
D
Q
1
A
1
DQU5
A2
DQU7
A3
DQU4
A7
V
D
D
Q
2
A
8
V
S
S
9
A
9
V
S
S
Q
1
B
1
V
D
D
1
B
2
V
S
S
8
B
3
DQSUn
B7
DQU6
B8
V
S
S
Q
2
B
9
V
D
D
Q
3
C
1
DQU3
C2
DQU1
C3
DQU0
D7
V
S
S
Q
4
D
8
V
D
D
3
D
9
V
S
S
1
E
1
V
S
S
Q
5
E
2
DQL0
E3
DML
E7
V
S
S
Q
6
E
8
V
D
D
Q
6
E
9
V
D
D
Q
7
F
1
DQL2
F2
DQSL
F3
DQL1
F7
DQL3
F8
V
S
S
Q
7
F
9
V
S
S
Q
8
G
1
DQL6
G2
DQSLn
G3
V
D
D
2
G
7
V
S
S
2
G
8
V
S
S
Q
9
G
9
VREFDQ
H1
V
D
D
Q
8
H
2
DQL4
H3
DQL7
H7
DQL5
H8
V
D
D
Q
9
H
9
NC4
J1
V
S
S
1
1
J
2
RASn
J3
CLK
J7
V
S
S
1
2
J
8
NC5
J9
ODT
K1
V
D
D
4
K
2
CASn
K3
CLKn
K7
V
D
D
5
K
8
CKE
K9
NC6
L1
CSn
L2
WEn
L3
A10/AP
L7
ZQ
L8
NC2
L9
V
S
S
3
M
1
BA0
M2
BA2
M3
NC1
M7
VREFCA
M8
V
S
S
1
0
M
9
V
D
D
6
N
1
A3
N2
A0
N3
A12/BCn
N7
BA1
N8
V
D
D
7
N
9
V
S
S
4
P
1
A5
P2
A2
P3
A1
P7
A4
P8
V
S
S
5
P
9
V
D
D
8
R
1
A7
R2
A9
R3
A11
R7
A6
R8
V
D
D
9
R
9
V
S
S
6
T
1
RESETn
T2
A13
T3
A14
T7
A8
T8
V
S
S
7
T
9
DQSU
C7
DQU2
C8
V
D
D
Q
4
C
9
V
S
S
Q
3
D
1
V
D
D
Q
5
D
2
DMU
D3
R7589
0R05 1/16W
C5282
1
0
0N
F
1
6V
R7588
0R05 1/16W
DDR3 DRAM
U5004
W631GG6MB-12
V
D
D
Q
1
A
1
DQU5
A2
DQU7
A3
DQU4
A7
V
D
D
Q
2
A
8
V
S
S
9
A
9
V
S
S
Q
1
B
1
V
D
D
1
B
2
V
S
S
8
B
3
DQSUn
B7
DQU6
B8
V
S
S
Q
2
B
9
V
D
D
Q
3
C
1
DQU3
C2
DQU1
C3
DQU0
D7
V
S
S
Q
4
D
8
V
D
D
3
D
9
V
S
S
1
E
1
V
S
S
Q
5
E
2
DQL0
E3
DML
E7
V
S
S
Q
6
E
8
V
D
D
Q
6
E
9
V
D
D
Q
7
F
1
DQL2
F2
DQSL
F3
DQL1
F7
DQL3
F8
V
S
S
Q
7
F
9
V
S
S
Q
8
G
1
DQL6
G2
DQSLn
G3
V
D
D
2
G
7
V
S
S
2
G
8
V
S
S
Q
9
G
9
VREFDQ
H1
V
D
D
Q
8
H
2
DQL4
H3
DQL7
H7
DQL5
H8
V
D
D
Q
9
H
9
NC4
J1
V
S
S
1
1
J
2
RASn
J3
CLK
J7
V
S
S
1
2
J
8
NC5
J9
ODT
K1
V
D
D
4
K
2
CASn
K3
CLKn
K7
V
D
D
5
K
8
CKE
K9
NC6
L1
CSn
L2
WEn
L3
A10/AP
L7
ZQ
L8
NC2
L9
V
S
S
3
M
1
BA0
M2
BA2
M3
NC1
M7
VREFCA
M8
V
S
S
1
0
M
9
V
D
D
6
N
1
A3
N2
A0
N3
A12/BCn
N7
BA1
N8
V
D
D
7
N
9
V
S
S
4
P
1
A5
P2
A2
P3
A1
P7
A4
P8
V
S
S
5
P
9
V
D
D
8
R
1
A7
R2
A9
R3
A11
R7
A6
R8
V
D
D
9
R
9
V
S
S
6
T
1
RESETn
T2
A13
T3
A14
T7
A8
T8
V
S
S
7
T
9
DQSU
C7
DQU2
C8
V
D
D
Q
4
C
9
V
S
S
Q
3
D
1
V
D
D
Q
5
D
2
DMU
D3
C5285
2
2U
F
6
.3
V
C5288
2
2U
F
6
.3
V
R7579
1K 1%
C5292
2
2
U
F
6
.3
V
C5279
1
0
0N
F
1
6V
C5300
1
0
0N
F
1
6V
TP7551
TP7553
C5290
1N 50V
R7582
240R 1%
C5228
100N 16V
C5294
N
C
/1
0
0
N
F
1
6
V
C5301
1
0
0N
F
1
6V
TP7556
R7591
NC/1K 1/16W 1%
R7576
NC/1K 1/16W 1%
C5296
1N 50V
R7587
1K 1%
R7577
100R 1%
TP7562
C5233
100N 16V
R7578
1K 1%
C5295
100N 16V
C5287
1
0
0N
F
1
6V
R7585
240R 1%
R7584
240R 1%
C5297
1
0
0N
F
1
6V
R7575
1K 1%
C5291
1
0
0N
F
1
6V
C5284
N
C
/1
0
0
N
F
1
6
V
C5298
1
0
0N
F
1
6V
C5280
N
C
/1
0
0
N
F
1
6
V
DDR_1.5V_AB
DDR_1.5V_AB
DDR_1.5V_CD
DDR_1.5V_CD
FRC_1.5V
DDR_1.5V_CD
DDR_1.5V_CD
DDR_1.5V_CD
DDR_1.5V_CD
DDR_1.5V_CD
NT334 DDR C-D
Updated on 2016/3/14
A_VREF
B_VREF
DDR Layout notice:
1. Please refer to AN01 (Layout Guide).
2. Reserve the solder Mask free for some DDR
signals. (use for DDR tester probe
connection)
CAP C5247~C5250
PLACE at Layer4,
just for debug
use.
DDR POWER CAP PLACE NEAR DDR IC
CL11(1600MHz)
CL11(1600MHz)
DDR_S_CS1N
B_VREF
DDR_S_CS0N
S_BA2
S_BA1
S_WEN
S_CASN
S_RASN
S_BA0
S_ODT
S_CS1N
S_CS0N
S_CKE
S_RSTN
DDR_S_ODT
C_DMU
C_DML
S_RSTN
S_CLKP
C_DQSLN
S_CLKN
C_DQSUP
C_DQSUN
C_DQSLP
DDR_S_CKE
S_BA1
S_BA2
S_BA0
S_A3
S_RASN
S_A0
S_WEN
S_A1
S_A8
S_A4
S_A5
S_A6
S_A7
S_A2
C_DQL1
C_DQL2
C_DQL0
S_A9
S_A13
C_DQL5
C_DQL6
C_DQL7
C_DQU0
C_DQL3
C_DQU4
C_DQU5
C_DQU1
C_DQU2
C_DQL4
C_DQU6
C_DQU7
C_DQU3
S_A5
S_A1
S_A0
S_A6
S_A9
S_A12
S_A4
S_A3
S_A2
S_A13
S_A8
S_A10
S_A11
S_A7
S_ODT
S_BA0
S_BA1
S_BA2
S_RASN
S_WEN
DDR_S_CKE
A_VREF
D_DQSUP
D_DQSLN
D_DQSUN
DDR_S_ODT
D_DQSLP
S_CLKP
S_CLKN
S_CASN
D_DMU
D_DQL0
D_DQL1
D_DQL2
D_DQL6
D_DQL7
D_DQL3
D_DQL4
D_DML
S_RSTN
D_DQU4
D_DQU3
D_DQU0
D_DQU1
D_DQL5
D_DQU6
D_DQU5
D_DQU7
D_DQU2
S_A10
S_A11
S_CLKN
S_CLKP
S_A12
DDR_S_CKE
DDR_S_CS0N
S_CKE
DDR_S_CS1N
DDR_S_ODT
S_CASN
S_CS1N
S_CS0N
C_DQL1
C_DQL2
C_DQL6
C_DQL3
C_DQL7
C_DQL0
C_DQL4
S_A0
S_A3
C_DQL5
S_A1
S_A2
S_A5
S_A6
S_A7
S_A4
S_A10
S_A11
S_A12
S_A8
S_A9
S_A13
C_DQU4
C_DQU2
C_DQSLP
C_DQSLN
C_DML
C_DQU5
C_DQU6
C_DQU0
C_DQU7
C_DQU1
C_DQU3
D_DMU
C_DQSUP
C_DQSUN
C_DMU
D_DQSUP
D_DQL5
D_DQL2
D_DQSUN
D_DQL1
D_DQL7
D_DQL4
D_DQU0
D_DQL6
D_DQL0
D_DQL3
D_DQU3
D_DQU2
D_DQU5
D_DQU6
D_DQU7
D_DQU1
D_DML
D_DQSLN
D_DQSLP
D_DQU4
S_CLKN
S_CLKP