10-7
Digital Main 3 Schematic Diagram
OPEN
C3009
0.1
C3012
OPEN
C3003
0.1
C3002
OPEN
C3005
L3001
OPEN
4.7K
R3007
33P
C3010
10K
R3002
D3002
MM5Z5V6B
D3003
MM5Z5V6B
D3004
MM5Z5V6B
10
C3008
100
R3006
0.1
C3004
47
R3005
0
R3001
4.7K
R3008
47
R3004
0
R3003
0.022
C3001
OPEN
C3006
0.1
C3007
33P
C3011
D3001
MM5Z5V6B
P-ON+3.3V
100
R9001
3 SDA
CN3002
1 IF-AGC
4 GND
2 SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
19
20
21
22
23
24
DSP
/FILTER
PGA
ADC
RF
AGC
OUTPUT
I/F
IC9001
SI2151
NU
SDA
SCL
IF-AGC
NU
GND
VDDL
GND
VCC
NU
XTAL-I
XTAL-O
VCC
GND
VCC
NU
RF-REF
RF-IP
GND
GND
NU
OPEN
C9019
1000P
C9008
1
C9009
1P
C9023
1000P
C9010
100
R9005
100
R9004
1P
C9021
1P
C9022
X9001
24MHz
1
3
4
2
82P
C9018
C9014
VARISTOR
150P
C9004
L9001
270nH
120P
C9002
L9002
220nH
180P
C9003
2P
C9015
L9007
5.6nH
1P
C9017
L9004
270nH
L9003
270nH
1000P
C9006
150P
C9005
L9006
270nH
L9005
270nH
1K
R9003
0.1
C9007
1000P
C9011
1000P
C9012
0.1
C9013
1
C9016
OPEN
C9020
100
R9002
JK9301
330P
C9001
OPEN
C9024
L3003
2.2uH
AM2
IC3001(3/9)
*1
MSD95M0D-3-005D
R5 TU-SDA
R4 TU-SCL
AK3 IF-AGC
0
L3002
AL2
AK1 NU
AK2 NU
AL7 NU
AM7 NU
AM8 NU
AK7 NU
AL5 NU
AM5 NU
33P
C3014
33P
C3013
OPEN
C9025
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
DEMODULATOR
/MPEG
DECODER
TO DIGITAL
MAIN 6
IC3001(6/9)
TO DIGITAL
MAIN 6
IC3001(6/9)
2
4
3
1
M
Q
O
N
P
R
DIGITAL MAIN CBA UNIT
CONTINUE
DIGITAL 9
(NO CONNECTION)
DIGITAL/ANALOG
TV TUNER
ANT-IN
The order of pins shown in this diagram is different from that of actual IC3001.
IC3001 is divided into nine and shown as IC3001 (1/9) ~ IC3001 (9/9) in this Digital Main Schematic Diagram Section.
1 NOTE:
PL17.06SCD3