IC Data Sheets
8.
8.8
Diagram
B15, MAX17113ETL (IC U7003)
Figure 8-10 Internal block diagram and pin configuration
18770_312_100217.eps
100217
Block diagram
Pinning information
MAX17113
THIN QFN
TOP VIEW
35
36
34
33
12
11
13
DVRP
SRC
GON
DRN
MODE
14
THR
DEL2
FSEL
V
IN
VL
EN2
PGND
IN2
IN2
1
2
SWI
4
5
6
7
27
28
29
30
26
24 23
22
SWO
FB1
BST
FB2
DEL1
REF
GND2
EN1
3
25
37
COMP
FBN
38
39
40
PGOOD
CRST
AGND
AGND
DRVN
CTL
LX1
32
15
LX2
LX1
31
16
17
18
19
20 LX2
DLP
FBP
CPGND
OUT
8
9
10
21
PGND
STEP-DOWN
OSC
VL
LX2
GND2
OUT
FB2
V
IN
REF
AGND
DEL1
VL
VL
V
IN
V
IN
(12V)
3.3V
2A
150mV
STEP-UP
POWER-UP
SEQUENCE
HV
SWITCH
BLOCK
NEGATIVE
REG
POSITIVE
REG
IN2
LX1
PGND
FB1
COMP
FSEL
AGND
SWI
SWO
PGOOD
PGOOD
3.3V
VL
BST
VGOFF
-6V
100mA
REF
VL
AV
DD
16V
1.5A
REF
DEL2
DLP
DRVN
FBN
FBP
REF
V
IN
CPGND
50% OSC
EN1
STEP-DOWN, NEGATIVE
ON/OFF
EN2
STEP-UP, POSITIVE
CHARGE PUMP ON/OFF
P
VGON
35V
50mA
DRN
THR
MODE
CRST
CTL
GON
CONTROL
GON
AV
DD
SRC
SWO
SRC
DRVP
CPGND
RESET