Philips 411EXP, Руководство по обслуживанию

Страница: 20 / 40

3-6
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
34 35 36 37 38 39 40 41 42 43 44
VDD2
UC1
UC2
UC3
UC4
UC5
N.C
NTEST
CLK
VSS
YSRDATA
NWE
D1
D0
D3
D2
NCAS
A10/ NCAS2
YMCLK
YMDATA
YMLD
YDMUTE
YLRCK
YSCK
ZSCK
ZLRCK
ZSRDATA
YFLAG YFCLK
YBLKCK NRESET
ZSENSE
VDD1
A3 A2 A1 A0 A4 A5 A6 A7 A8 A9
NRAS
S
M
590
3B
F
Pin number Pin name I/O Function Setting
H L
1 VDD2 - VDD supply pin
2 UC1 Ip/O Microcontroller interface extension I/O 1
3 UC2 Ip/O Microcontroller interface extension I/O 2
4 UC3 Ip/O Microcontroller interface extension I/O 3
5 UC4 Ip/O Microcontroller interface extension I/O 4
6 UC5 Ip/O Microcontroller interface extension I/O 5
7 N.C -
8 NTEST Ip Test pin Test
9 CLK I 16.9344 MHz clock input
10 VSS - Ground
11 YSRDATA I Audio serial input data
12 YLRCK I Audio serial input LR clock Left channel Right channel
13 YSCK I Audio serial input bit clock
14 ZSCK O Audio serial output bit clock
15 ZLRCK O Audio serial output LR clock Left channel Right channel
16 ZSRDATA O Audio serial output data
17 YFLAG I Signal processor IC RAM overflow flag Overflow
18 YFCLK I Crystal-controlled frame clock
19 YBLKCK I Subcode block clock signal
20 NRESET I System reset pin Reset
21 ZSENSE O Microcontroller interface status output
22 VDD1 - VDD supply pin
23 YDMUTE I Forced mute pin Mute
24 YMLD I Microcontroller interface latch clock
25 YMDATA I Microcontroller interface serial data
26 YMCLK I Microcontroller interface shift clock
27 A10 O DRAM address 10
(NCAS2) O DRAM2 CAS control (with 2 DRAMs)
28 NCAS O DRAM CAS control
29 D2 I/O DRAM data input/output 2
30 D3 I/O DRAM data input/output 3
31 D0 I/O DRAM data input/output 0
32 D1 I/O DRAM data input/output 1
33 NWE O DRAM WE control
34 NRAS O DRAM RAS control
35 A9 O DRAM address 9
36 A8 O DRAM address 8
37 A7 O DRAM address 7
38 A6 O DRAM address 6
39 A5 O DRAM address 5
40 A4 O DRAM address 4
41 A0 O DRAM address 0
42 A1 O DRAM address 1
43 A2 O DRAM address 2
44 A3 O DRAM address 3
Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when in input mode)
Control
Input 1
Control
Input 2
Micro-
controller
Interface
General
Port
Output Interface Input Interface
Input Buffer
Decoder Encoder
DRAM Interface
YBLKCK
YFCLK
YFLAG
YMDATA
YMCLK
YMLD
ZSENSE
UC1 to UC5
YDMUTE
NRESET
NTEST
CLK
NRAS
NCAS
NCAS2
NWE
A0 to A10
D0 to D3
Through
Mode
Compression
Mode
ZLRCK ZSCK
ZSRDATA YLRCK YSCK YSRDATA
7800 : SM5903BF