10-10
C24 UART0TX
N24 USB0OD
N23 USB0VBUS
N22 USB0(-)
M24 USB0(+)
OPEN
D3001
OPEN
C3003
AB9
NU
AE9
AD9
AA13
IF-AGC
Y15
TU-SCL
AA16
TU-SDA
Y12
NU
AA15
NU
33
R3006
33
R3007
39P
C3013
L3003
3.3uH
0.1
C3011
0.1
C3014
L3004
3.3uH
OPEN
C3010
OPEN
C3002
OPEN
D3002
C3739
1
L3706
OPEN
1
2
3
4
5
IC3701
AP2151WG-7
VOUT
GND
/FLAG EN
VIN
AB8 NU
K23 NU
K24 NU
P-ON+3.3V
4
GND
CN3704
1
USB+5V
3
USB0(+)
2
USB0(-)
TU3001
TUNER UNIT
1
+3.3V
2
GND
3
SDA
4
SCL
5
IF-AGC
6
DIF-OUT1
7
DIF-OUT2
OPEN
D3010
270
R3005
270
R3003
OPEN
C3026
OPEN
C3027
OPEN
C3117
UARTOTX 2
100
R3175
R3101
10K
UARTORX 3
E22 UARTOTX
R3108
OPEN
100
R3176
P-ON+5V 1
CN3101
GND
4
OPEN
C3116
C3742
220/6.3V
R3761
10K
100
R3758
0.1
C3727
2.49K
R3172
10k
R3177
OPEN
C3115
AC9
NU
W14
NU
W10
NU
MM5Z5V6B
D3007
OPEN
C3039
10
C3040
OPEN
C3041
L3005
2.2uH
4.7K
R3011
4.7K
R3025
P-ON+5V
10K
R3001
0.1
C3009
10K
R3004
Y13
NU
W8
NU
AA8
NU
4
GND
CN3701
1
USB1(+)
CN3705
4
USB+5V
3
USB+5V
3
USB1(-)
2
USB1(+)
2
USB1(-)
6
GND
5
GND
1
GND
L3701
OPEN
L23 USB1(+)
M22 USB1(-)
M25 USB1VBUS
C3716
OPEN
1
2
3
4
5
IC3702
OPEN
VOUT
GND
/FLAG EN
VIN
OPEN
R3702
R3704
OPEN
C3715
OPEN
OPEN
C3714
0
R3734
0
R3736
R3735
OPEN
UART1RX
UART1TX
100
R3194
G20 UART1TX
1K
R3217
100
R3193
F21 UART1RX
M1
IC3101(4/7)
*1
MN2WS0270EA
NU
N4
NU
M2
NU
P5
NU
B25 NU
D23 NU
R6 RX(-)
R2 TCT
C3701
0.01
R1 TX(+)
CN3706
R8 GND
C3744
0.01
R3 TX(-)
R5 RCT
R7 NU
R4 RX(+)
AC8
RX(-)
AC7
RX(+)
AE6
TX(-)
AD6
TX(+)
U10
NU
AC6
CTRL11
CTRL11
C3129
1
0.1
C3008
10K
R3180
M23 USB10D
Z
AC
1
4
2
AB
Y
AA
3
AD
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
CONTINUE
DIGITAL 7
TO DIGITAL
MAIN 6
IC3101(5/7)
TO DIGITAL
MAIN 6
IC3101(5/7)
DEMODULATOR
/MPEG
DECODER
DIGITAL MAIN CBA UNIT
(USB JACK)
(HIGH SIDE SWITCH)
(NO CONNECTION)
(NO CONNECTION)
WIRELESS
LAN MODULE
(ETHERNET JACK)
CONTINUE
DIGITAL 8
CONTINUE
DIGITAL 7
Digital Main 5 Schematic Diagram [TYPE A]
PL13.11ASCD5
The order of pins shown in this diagram is different from that of actual IC3101.
IC3101 is divided into seven and shown as IC3101 (1/7) ~ IC3101 (7/7) in this Digital Main Schematic Diagram Section.
1 NOTE: