IC Data Sheets
8.
8.5
Diagram
B16, TC90537FG (IC U101)
Figure 8-7 Internal block diagram and pin configuration
19480_304_130409.eps
130409
Block diagram
Pinning information
G
F
7
3
5
0
9
C
T
S
RCK
PBV
A
L
S
RDT
S
LOCK
RLOCK
RERR
S
LPEN
GPIO2
GPIO1
GPIO0
V
SS
VDDC
12 11
10 9
8
7
6
5
4
3
2
1
VSS
13
48 VDDS
VDDS
14
47 VSS
RSEORF
15
46 SDA
SBYTE
16
45 SCL
SLADRS0
17
44 STSFLG0
AGCCNTI
18
43 STSFLG1
AGCCNTR 19
42
SYRSTN
TNSCL
20
41
VPGM
TNSDA
21
40 AINN Q
XCKO
22
39 AINP Q
XO
23
38 AINN
I
XI
24
37 AINP I
25 26 27 28 29
30
31
32
33
34
35
36
PLL
VDD
PLL
V
SS
VD
DC
CKI
S
LADR
S
1
T
S
MD
V
SS
VD
DC
A
DCV
DD
A
DCV
SS
VREFL
VREFH
G
F
7
3
5
0
9
C
T
Synchroni-za
tion flag
TS output
Crystal
(reference clock)
Tuner
AGC
control
IIC
control
Filter
AGC
ISIC
(unguarded
pre/post echo
suppression)
FFT
Control
Adaptive
interpolation
filter
Equalization
(With Doppler
Compensation
)
CSI
(Reliability
detection)
CVI
(CW interference
detection)
AGC control output
Tuner IIC
Clock PLL
Viterbi
decoding
Memory
Frequency
deinterleaving
RS
decoding
Error
detection
Output
control
Layer
isolation
TMCC
demodulation
Interpolation
phase
Correction
Synchroni
zation
Demapping
CSI
processing
Bit deinter
le
a
ving
B
y
te deinter
le
a
vin
g
T
S
m
u
ltiple
x
FFT window
control
ADC
ADC
IF input
or IQ input
SW
External AGC input
Host IIC
Energy
despreading
Energy
despreading
Energy
despreading
Demapping
CSI
processing
Demapping
CSI
processing
Mod
u
la
tion divi
s
ion
Quadrature
detection
AFC
Frequency
CPE
Pilot
extraction
Time
deinterleaving