PEP CP381, Руководство пользователя

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Configuration CP381
Page 4 - 6 © 2002 PEP Modular Computers GmbH ID 24107, Rev. 01
4.3 Programming Interface
4.3.1 Access Control Logic (Address Decoder)
All the resources of the CP381 are mapped within the 64 kB PCI memory address space which
itself is set in the PCI configuration register BAR0. The port size of all local or backend registers
is 32-bit by default. The address map of the registers is as follows.
Table 4-1: Backend Register Address Map
Base Address Size Function
bar0 + 0x0000 4 K Common Board Registers
0x0400 32 bit g_irq General Interrupt Enable Register
0x0800 32 bit hsr Hardware Status Register
0x0804 32 bit i_pen General Interrupt Pending Register
0x0c00 32 bit hdr Hardware Debug Register
bar0 + 0x1000 4 K Capability ROM, serial EEPROM
0x1000 32 bit r_cmd Command Register
0x1400 32 bit r_ctl Control Register
0x1800 32 bit r_sta Status Register
0x1c00 32 bit r_dat Data Register
bar0 + 0x2000 2 K Input Control
0x2400 32 bit i_ctl Input Control Register
0x2408 32 bit i_irqen Input Irq Enable Register
0x240c 32 bit e_pol Input Event Polarity Register
0x2410 32 bit e_msk Input Event Mask Register
0x2414 32 bit e_len Input Latch-on-Event Register
0x2418 32 bit c_cmp Input Pattern Compare Register
0x241c 32 bit c_msk Input Pattern Mask Register
bar0 + 0x2800 1 K Input Status
0x2800 32 bit i_event, Input Status Register
bar0 + 0x2c00 1 K Input Data
0x2c00 32 bit d_in, Input Data Register
0x2c04 32 bit input, Transparent Input Data
bar0 + 0x3000 – 0xffff 52 K Reserved