Backplane architecture
30
Model 6276 User Guide
3 • System architecture
3U and 6U cards use a single 220 pin connector for all power, ground, and all 32- and 64-bit PCI signals. This
connector consists of two halves—the lower half (110 pins) is called J1/P1 and the upper half (also 110 pins) is
called J2/P2. Twenty pins are reserved for future use. The connector is divided in J1/P1, a 25-row connector
that includes voltage keying, and J2/P2, a 22-row connector without keying. The 2U card can have up to four
additional connectors with a total of 315 pins, which can be used for a variety of purposes.
A system CPU uses J1 and J2, but 32-bit peripherals cards only need to use J1 for full CompactPCI function-
ality. J3 through J5 on 2U cards can be user-defined I/O. Optional buses, such as the CT H.110 bus, use the
J4 position.
J1/P1 & J2/P2 connectors
The CompactPCI bus spans the J1/P1 & J2/P2 connectors, with 32-bit PCI implemented on J1/P1 and full
64-bit PCI implemented on J2/P2 on the Model 6276 Midplane. J1/P1 is always devoted to 32-bit PCI in
CompactPCI systems, however, use of J2/P2 for 64-bit PCI can be optional. For instance, J2/P2 may be
defined for user I/O, or sub-buses like the CT H.110 bus. J2 is always used on system slot boards to provide
arbitration and clock signals for peripheral boards.
J3/P3 through J5/P5 connector
J3/P3 through J5/P5 connectors, available only in 2U systems, are generally defined for user I/O. However,
sub-bus interconnects (for example, CT H.110 bus) can be configured on the J4/P4 connector.
Reserved pins
There are bused and non-bused reserved pins as noted below:
•
The BRSVPxxx signals SHALL be bused between connectors and are reserved for future CompactPCI def-
inition.
•
The RSV signals are non-bused signals that shall be reserved for future CompactPCI definition.
Power pins
The 2U Model 6276 Backplane/Midplane has a selectable signaling environment. All connectors on the 2U
Model 6276 Backplane/Midplane provide pins for +5V, +3.3V, +12V and -12V operating power. In addition,
there are power pins lV(I/O). The V(I/O) power pins on the connector are used to power the buffers
on the peripheral boards, allowing a card to be designed to work in either interface.
In a ForeFront environment, the V(I/O) pins must always be configured for 3.3 VDC. This is selected by a
strap on the mid-plane.
Backplane architecture
Patton Electronics Company, 2U Model 6276 Backplane/Midplane provides one CompactPCI bus segment.
The cPCI bus segment is composed of four 6U board locations (at 33 MHz) with 20.32 mm (0.8 inch) board
center-to-center spacing. The 6U cards are stacked horizontally in the 2U model, however, the special design pro-
vides vertical convection cooling with the installed plug-in fan tray module (See Fan Tray Assembly on page 22).
