Paradyne ACCULINK 3161, Быстрая справка

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Table 2. Port Configuration Options (2 of 3)
Option Comments/Description Factory 2 Factory 1
Disab Disab
Net DCLB:
V.54 V.54
Network-initiated DCLB, allows
DCLB to be controlled by inband
Net DCLB:
FT1 FT1
,
DCLB to be controlled by inband
V.54 or FT1 (ANSI) codes.
Both Both
Disab Disab
Port LB:
DTLB DTLB
Port-initiated Loopbacks, allows
Loopbacks to be initiated through
Port LB:
DCLB DCLB
p ,
Loopbacks to be initiated through
the port by the external DTE.
Both Both
p y
Disab Disab
All Ones:
DTR DTR
All ones sent to network (DTE) T1
All Ones:
RTS RTS
All ones sent to network (DTE) T1
when DTR or RTS interrupted.
Both Both
Rcv Yellow:
None None
Data port remains enabled, or is
disabled on receiving Yellow on
Rcv Yellow:
(Received Yellow)
Halt Halt
p ,
disabled, on receiving Yellow on
network T1.
Tx Clock:
Int Int
Selects whether the transmitted
data clock is internal (TXC) or
Tx Clock:
Ext Ext
data clock is internal (TXC) or
external (XTXC).
InvertTxC:
Enab Enab
Selects phase inversion of the InvertTxC:
(Invert Tx Clock)
Disab Disab
Selects phase inversion of the
transmit clock (TXC).
InvertData:
Enab Enab
Allows the data on the port to be
InvertData:
Disab Disab
Allows the data on the port to be
inverted.
EDL:
Enab Enab
Specifies whether the Embedded
EDL:
Disab Disab
Specifies whether the Embedded
Data Link is enabled.