22
Pin Name
I/O Description
122 GND
–
Ground terminal.
123 DFULZA
O
DFULZA signal output terminal.
124 ORUNA
O
ORUNA signal output terminal.
125 BFMPZA
O
BFMZA signal output terminal.
126 RX/TXZA
I
RX/TXZA signal input terminal.
128 CHSLA1
I
CHSLA1 signal input terminal.
127 WENZA
O
Write Enable signal output terminal.
129 CHSLA2
I
CHSLA2 signal input terminal.
130 CHSLA3
I
CHSLA3 signal input terminal.
131 CHSLA4
I
CHSLA4 signal input terminal.
132 SYNC16
I
16CH Sync signal input terminal.
133 DIN16
I
16CH Data input terminal.
134 DOUT16
O
16CH Data output terminal.
135 IFCP16
O
16CH IF Clamp Pulse output terminal.
136 DGP3_16
O
16CH DGP3 signal output terminal.
137 GND
–
Ground terminal.
138 SYNC15
I
15CH Sync signal input terminal.
139 DIN15
I
15CH Data input terminal.
140 DOUT15
O
15CH Data output terminal.
141 IFCP15
O
15CH IF Clamp Pulse output terminal.
142 DGP3_15
O
15CH DGP3 signal output terminal.
143 SYNC14
I
14CH Sync signal input terminal.
144 DIN14
I
14CH Data input terminal.
145 DOUT14
O
14CH Data output terminal.
146 IFCP14
O
14CH IF Clamp Pulse output terminal.
147 DGP3_14
O
14CH DGP3 signal output terminal.
148 GND
–
Ground terminal.
149 SYNC13
I
13CH Sync signal input terminal.
150 DIN13
I
13CH Data input terminal.
151 DOUT13
O
13CH Data output terminal.
152 IFCP13
O
13CH IF Clamp Pulse output terminal.
153 DGP3_13
O
13CH DGP3 signal output terminal.
154 SYNC12
I
12CH Sync signal input terminal.
155 DIN12
I
12CH Data input terminal.
156 DOUT12
O
12CH Data output terminal.
157 IFCP12
O
12CH IF Clamp Pulse output terminal.
158 DGP3_12
O
12CH DGP3 signal output terminal.
159 GND
–
Ground terminal.
160 GND
–
Ground terminal.
L
H
INPUTS
A Data to B Bus
OPERATION
:
Don’t care.
L
G
L
B Data to A Bus
Truth Table
DIR
Isolation
H
DIR 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
20 Vcc
19 G
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
(TOP VIEW)
A8 9
GND 10
11 B8
12 B7
∗
∗
2.2.
IC60 on the Main Board is using the Octal 3-State
Inverted Bus Transceivers IC MC74AC640DT.
Description of this IC is as follows:
