15.34. DT-Board (2 of 2) Block Diagram
EA2
VSYNC
ADIN
SCL_TV
L_OUT
R_OUT
MAIN_SW
TDI/PEAKS
AFT
XRST
MAIN_R
TRST
POWER_DET
SBO1
SBI1
VIDEO_OUT
MAIN_L
HSYNC
CLK
SLRCK
SDA_TV
MPEG_PKT_SYNC
SCHDATA0
SCHCLK0
SER_DATA
TMS
POD_DRX
MPEG_DATA_EN
POD_CRX
TO_DT12
TRST
XP0DIRQ
TO_ASIC
XEDK
ENABLE0
XERE
PSYNC0
XEWE2
XECS3
MPEG_CLK
ECLK
TCK
XPODRST
MPEG_ERR
XP0DIRQ
XEDK
XEWE0-3
ECLK/ECLK1
XERE
XECS0-5
XPODRST
SCHCLK0
SCHD
A
T
A
0
ENABLE0
PSYNC0
TRST
TO_FRONT/SBI0
TO_SID6/SBO0
TCK
TMS
XEDK
XEWE3
XCS2
XERE
XECS4
XEWE2
XRST
XVBIRST
ESZ0
ADCRST
ESZ1
XRST
OUT
ECLK
XRST
XEDK
TDO/ASIC
TMS
TCK
XSPTIRQ
ERXW
SRQ
XEAS
XNMIRQ
XECS0-5
TMS
TCK
SBI0/T
O_PEAKS
SBO0/T
O_SID6
XRST
IRST
ESZ0-1
ERXW
XEAS
XSPTIRQ
XNMIRQ
XERE
XEWE3
XEWE2
ESZ1
ESZ0
SBI0
SBO0
ECLK
SRQ
SRQ
PO
WER_DET
SBI1
SBO1
HSYNC
VSYNC
CLK
X8006
HDsL PEAKS
IC8013
TD2S
MCP2L
AM33(200MHz)
NTSC ENC.
PERIPHERAL
VIDEO DAC
AVR 1.8V
VIN
VOUT
IC8218
+1.8V
5
+3.3V
1
10
2ch SWITCH
VPPOUT
5V_SUB
12
POWER MANAGEMENT
1
11
IC8250
4
3
9
EN0
5VIN 15
2
EN1
3VIN
13
3VIN
3VIN
3VIN
3VIN
VPPOUT
3.3V
3.3V
5V
L
H
L
H
VPP EN0 EN1
TRST(JTAG_TRST)
MHSYNC0
SCL1
37
(SW_OFF)
MVC0
MVC7
10
60
LRCK
13
SD
A0
Q8010
SCL0
SD
A1
SCL1
+3.3V
SDA1
D8208
DIGITAL
MVY0
3.3V
SUB 5V
85
CLK
HSYNC
MVC7
16Bit AUDIO ADC
MVY7
58
IC8244
MVC0
54
MVY7
30V
+1.8V
1
3
PDN
9
SUB 9V
SDTO
109
47
53
96
AINR
88
97
1
105
MVCLK0(PEAKS_CLK)
SCL1
2
80
MHSYNC0(PEAKS_H)
VSYNC
MVSYNC0(PEAKS_V)
DC(BS_C)
45
DY(BS_Y)
87
32
SBO1(RXD1)
MAIN_L
106
DC
IN
SCL1(DTV_SCL0B)
18
MVY0
(SDA0B)
107
SBI1(TXD1)
TDI(TO PEAKS)
IEC_OUT
SD
A0
MVC7 (PEAKS_C7)
19
41
30V(BT30V)
MVC0 (PEAKS_C0)
DG22
8
AUDIO OUT
MVY7 (PEAKS_Y7)
43
SUB 9V
DC
OUT
33
MVY0 (PEAKS_Y0)
51
IC8055
L_OUT(BS_SL)
AVR 1.8V
52
SD
A1
SDA1(DTV_SDA0B)
SUB 9V
(SCL0B)
13
AINL
AFT(AFT1)
36
9V_SUB
R_OUT(BS_SR)
ADIN
5V_A
29
TO
SCL0
MAIN_R
SLRCK
5V_SUB
34
POWER_DET
MVCLK0
SDA_TV
SUB 5V
Q8011
35
MAIN_SW
22
XRST(DTV_RST)
VIDEO_OUT
SCL_TV
57
DT12
15
30
MVSYNC0
A0-A3
22
POD ASIC
130
105
37
(IOIS16)
DATA BUS
FE_DATA
+3.3V
(A16,A17)
RESETn
128
TRST
MDI4-MDI7
(A4,A7)
(D11-D15)
BE_DATA
A10,A11
(A6,A5)
16
34
54
EN_VPP5
MIVAL,MISTRT
6
51
(A8,A9)
ED7
RESET,REG
INTN
15
45
FE_SYNC
30
TCK
XECS
120
BE_CLK
MOD D0-D7
ETX,ITX
EA
FE_ERR
144
138
143
141
(A8,A9)
A0
Cable CARD
A25
21
117
(A14,A15)
A12,A13
3
(A16,A17)
8
MOD MDO0-MDO7
ED16-ED23
(A18-A25)
9
124
CD1n,CD2n
(READY)
MDO0-MDO2
EN_VPP3
56
CTX,QTX
MCLK0,MCLK1
53
142
14
MDI0-MDI3
126
47
(MOSTRT)
TMS
JTAG
32
CRX,DRX
XEWENO
MCLK0,MCLK1
26
CE1,CE2
TDO
24
131
133
MDI0-MDI7
18
49
BE_SYNC
109
MDO3-MDO7
122
63
5V
(A4,A5)
ADDRESS BUS
MIVAL,MISTRT
CONTROL BUS
66
10
CONTROL BUS
D3-D7
61
11
DATA BUS
IORD,IOWR
DT04
67
36
29
IC8216
TDI
ETX,QTX
1
8
BE_EN
CE1,CE2
FE_CLK
9
ECLK
D0-D2
REG,RESET
56
A0-A3,A10-A13
FE_CRX
MOSTRT(BVD2)
ED0
IOWR,IORD
60
(A6,A7)
(D8-D10)
CRX,DRX
33
13
CTX,ITX
IREQ,WAIT
3.3V
OE,WE
17
20
59
23
(A22-A25)
44
BVD2,
52
58
7
12
46
2
(MOVAL)
(A14,A15)
WP,INPACK
64
132
19
42
62
CLKIN133
50
FE_EN
WP,INPACK
41
WAIT,IREQ
140
BVD2
MOVAL(BVD2)
CD1,CD2
WE,OE
(A18-A21)
60
51
XEREN
XEDKN
4
25
FE_DRX
2
3.3V
IC8043
OUT
4
VDD
RESET2
SBO0
ED16
SBI0
EA0
CARD
ED31
DT08
XEWE2
ED26
81
65
88
101
87
110
8
82
24
43
1
10
103
84
30
46
83
SRQ
XEDK ASIC
ASIC_RESET
XEWE0-3
XECS0-5
XIRQ16
ECLK ASIC
XERE
PSYNC0
CHBAL0
CHD
A
T
A
0
CHCLK0
29
26
27
ESZ0
ESZ1
70
41
XEWE3
XERE
44
XEDK
39
77
34
XECS0
XECS5
32
79
XEAS
74
36
35
XRST
72
ECLK
67
ERXW
XSPTIRQ
45
66
XNMIRQ
JTAG
ADDRESS BUS
DATA BUS
XRST
XCS2
WD0
50
43
42
5
TDO
89
TRST
DATA16
DATA31
21
TCK
91
TMS
ED16-ED31
XEDK
IC8026
90
RD
SID6
47
49
44
48
92
93
XCS4
TDI
WD1
AD0
AD11
40
24
SRQ
95
199
198
74
PWDN
XVBIRST
112
ESZ1
ESZ0
XRST
PO
WER_DET
XRST
OUT
2
XRST
9V_SUB
IC8042
OUT
4
VDD
RESET
XRST
28
TDO
TMS
27
TCK
26
+3.3V
5V_SUB
SUPPORT
HC06
DT07
+5V
SBI0
3
1
5V_SUB
2
SBO0
TO
XWP,XNWE1
NALE1,NCLE1
XNCE1
XNRE1
NRXB1
210
214
4
3
XFERST
SBI0/TDI
SBO0/TD0
SBT0TCK
TMS
DQ0-DQ15
A0-A21
XRST
EA1-EA22
IC8019
ED16-ED31
TRSTEN
ESZ0-1
XEAS
ERXW
XNMIRQ
XSPTIRQ
CE,OE,WE
RESET
IC8038
ED16-ED31
128M WORK CPU FLASH
I/O1-I/O16
RY/BY,RE,CE
CLE,ALE,WE,WP
CPU FLASH
ROM I/F
XEREL
EA26
EA1
XECS0L
XEWE2
ED31
ED16
CONTROL BUS
ADDRESS BUS
AVDDMPLL
VDD33
AVDD33UPLL
AVDDAPLL
AVDDRAC
AVDDUPLL
VDD15
+1.5V
VDDIC
VREFRAC
VREF RAC1.4V
AVR 2.5V
VIN
VOUT
IC8044
+2.5V
1
+3.3V
6
AVR 2.5V
+3.3V
IC8220
1
VOUT
VIN
+2.5V
5
5
VDD
2
CLK
X1
16
X2
1
IC8249
CLOCK GEN
+3.3V
18
RESET
15
SCL
16
SDA
LOSD14
MVY0
LOSD0
MVY7
88
LOSD0
96
LOSD14
HDsL_PEAKS(1/5)
HDsL_PEAKS(3/5)
POWER SUPPLY
JTAG/
SERIAL
CHANNEL
HDsL_PEAKS(5/5)
68
IIC BUS
DATA BUS
DATA BUS
ADDRESS BUS
DATA BUS
CONTROL BUS
CONTROL BUS
11
41
SYSCLK
2
D0
D7
22
C/V
20
Y
NTSC ENCODER
IC8030
SCL1
SDA1
5V_FDC
114
NTSCRST
FORMAT_EDGE
117
24
FORMAT EDGE
SVD7
SVD0
SVCLK0
OSD
74
115
PDN
PWDN
(FROM AUDIO DAC)
DACRST
ADCRST
(FROM AUDIO ADC)
ADCRST
(TO SID6)
EA2
64M CPU
FLASH ROM
5
4
3
2
1
ECLK 33.75MHz
52
AD21
AD24
SRQ
23
SBO1
SBI1
HDsL_PEAKS
(2/5)
L
VSYNCI
ISOSYNC
LOSKI
LOSDYS
107
LOSDYM
106
LOSD_YM
LOSD_YS
TH-65PX600U
DT-Board (2 of 2) Block Diagram
TH-65PX600U
DT-Board (2 of 2) Block Diagram
TH-65PX600U
114
Содержание TH-65PX600U
Страница 5: ...1 Applicable signals 5 TH 65PX600U ...
Страница 23: ...8 Location of Lead Wiring 8 1 Lead of Wiring 1 23 TH 65PX600U ...
Страница 24: ...8 2 Lead of Wiring 2 24 TH 65PX600U ...
Страница 25: ...8 3 Lead of Wiring 3 25 TH 65PX600U ...
Страница 26: ...8 4 Lead of Wiring 4 26 TH 65PX600U ...
Страница 27: ...8 5 Lead of Wiring 5 27 TH 65PX600U ...
Страница 32: ...9 4 No Picture 32 TH 65PX600U ...
Страница 39: ...11 4 Adjustment Volume Location 11 5 Test Point Location 39 TH 65PX600U ...
Страница 41: ...41 TH 65PX600U ...
Страница 80: ...NOTE TH 65PX600U 80 ...
Страница 81: ...15 Schematic and Block Diagram 15 1 Schematic Diagram Notes TH 65PX600U 81 ...
Страница 163: ...16 Parts Location Mechanical Replacement Parts List 16 1 Parts Location 163 TH 65PX600U ...
Страница 164: ...16 2 Packing Exploded Views 164 TH 65PX600U ...
Страница 165: ...16 3 Packing Exploded Views 165 TH 65PX600U ...
Страница 167: ...17 Electrical Replacement Parts List 17 1 Replacement Parts List Notes 167 TH 65PX600U ...