Panasonic TH-103PF9EK, Руководство по обслуживанию

Страница: 96 / 121

13.20. DN-Board (3 of 3) Block Diagram
P3V_SCL2
P3V_SDA2
P3V_SD
A2
P3V_SCL2
STB+5V
+1.2V +3.3V
P5V_DC2
P+15V
+2.5V
STB+5V STB+1.5V
P5V_DC
+3.3V
+1.2V
Q4718
P5V_DC1
Q4717
+1.8V
+3.3V
STB+3.3V
18
TB+
59
O-LVDS1
TTL
20
G1
O+LVDS0
VO
E-LVDS3
O-LVDS0
TC-
VOUT
TCLK+
VDD
IC4309
9
22
OUT2
E+LVDS0
17
VO
21
G2
D2
33
L
VDS
O+LVDS4
E-LVDS4
16
NRST
O-LVDS4
4
GOE0-9
26
21
31
(SERIAL)
31
22
19
GC_CLKIN
13
31
GC_HSIN
D2
GC_VSIN
8
13
52
6
OUT1
VOUT
19
57
D2
14
STB 3.3V
E+LVDS4
1
TA-
VOUT
CTL
12
38
DC-DC CONVERTER
E-LVDS0
38
5
P
ARALLEL
25
CLK7425
S1
54
VOUT
NRST
-FP
FB
TCLK-
IC4004
L
VDS-PD
VIN
40
FHQCKIN
33
S1
VCOIN
61
16
29
TC-
+1.8V
16 OUT2
9
ROE0-9
+2.5V
Q4306
30
FHQCIN0-9
[EVEN]
D1
P+15V
5
L
VDS
PO_FLD
9
62
9
VCC
P+15V
PO_RE0-9
-INC
46
VIN
[ODD]
D1
S2
CB
44
5
D
ATA
TD-
TB-
TE-
AVR 5V
Q4303
VDD
DN
51
D1
24
19
4
O-LVDS2
O+LVDS3
HSYNC
28
D1
IC4303
LVDS OUT[ODD]
5
CLKIN
24
P+15V
LVDS OUT[EVEN]
VCC
D2
CTL
21
42
4
63
E+LVDS3
VCC
E-LVDS2
11
23
19
CTL
23
LX
LVDS
TRANSMITTER
(10bit)
23
5
48
64
18
30
IC4304
-INC
22
IIC_BUS
59
CLKM_20MHz
1.2V REG
62
10Bit LVDS
ROUT
CLK7425-1
VIN
VDD
TC4
VSYNC
LX
50
TE+
CLK_O
G2
VOUT
48
55
S1
21
9 CTL
P
ARALLEL
8
VDD
15
OUT2
27
G1
1
-INC
P_ON/OFF
GC5 PROCESOR
GC_HD
FPGA_NCONFIG
21
26
18
28
FHQYIN0-9
IC4001
GC_CLK
FPGA_DCLK
IC4307
IIC_BUS
20
8
GC_RGB IN
FPGA_DCLK
D
ATA
44
55
21
19
HSYNC
25
SCL
20
O+LVDS2
24
/PDWN
D1
VDD
GOUT
AVR 5V
CLK_O
CONFIGURATION
D1
5
BOUT
+1.5V
VSYNC
1
GC_GIN0-9
VO
LVDS
TRANSMITTER
(10bit)
GC_RIN0-9
VIN
ROUT
18
OUT1
VSOE
GC_BIN0-9
PORT-FHQ
54
BOUT
IC4305
DC-DC CONVERTER
CLKOE
PO_GO0-9
(GC3E & HQ1)
GOUT
24
PO_BO0-9
20
4
PO_R
O0-9
50
24
17
21
18
IC5802
9
1
16
5
10Bit LVDS
G1
52
IC4306
D2
Q4301
PO_VS
E+LVDSCLK
PORT-E
/PDWN
TD-
[EVEN]
20
11
6
PO_HS
RGB 30bit OUT
PO_GE0-9
PO_A
CT
E-LVDS1
TA-
PO_BE0-9
TC5
D2
BOE0-9
1
5
TC+
G2
E-LVDSCLK
HSOE
IC4308
CLK3
FB
13
OUT2
NRST
LX
23
STB 1.5V
TE-
VDD
20
SD
A
DC-DC CONVERTER
24
TB-
GC_YO0-9
46
20
S2
VO
GC_CO0-9
FHQHIN
13
FPGA_DATA0
GC_VD
23
23
-INC
FHQVIN
OUT1
IC5801
TO D5
FPGA_NSTATUS
6
FPGA_CONFDONE
D1
TC5
S2
19
TB+
24
63
13
OSD IN
57
+3.3V
O-LVDS3
G1
D1
OSD_HDO
O+LVDS1
P+15V
OSD_VDO
CLKIN
15V->2.5V
VDD
[ODD]
G2
29
11
O+LVDSCLK
13
TC+
1
15V->1.8V
64
I-CHIPS RGB IN
17
IC5301
1
S1
15V->1.5V
FPGA3
TA+
29
17
23
TD+
25
5
17
23
TCLK-
CB
24
15V->3.3V
CB
10
TD+
DC-DC CONVERTER
S2
CLK1
OSD-HD
21
CLK0
7
TE+
+1.5V
OSD_DATA0-15
42
E+LVDS1 TTL
TA+
PO_CLK
12
30
+2.5V
CB
GC_YC OUT
OUT1
VIN
5
+3.3V
2
61
5
9
TC4
FB
18
IC4301
VCC
D2
40
12
LX
D2
18
VIN
Q4302
(SERIAL)
OSD_YS
25
OSD_YM
FB
28
TCLK+
O-LVDSCLK
E+LVDS2
OSD_CLK
DIGITAL SIGNAL PROCESSOR/MICOM !
DN
(Exchange board only)
<TZTNP01YLTU>
TH-103PF9UK/EK
DN-Board (3 of 3) Block Diagram
TH-103PF9UK/EK
DN-Board (3 of 3) Block Diagram
TH-103PF9UK / TH-103PF9EK
96